Pushing the performance limits due to power dissipation of future ULSI chips

The trend of power dissipation in current and future commercial CMOS integrated circuits is investigated considering that the minimum device size may scale down to about 0.1 mu m in the next decade. The power dissipation trend makes clear that it will be necessary to come up with some new concepts to reduce the power dissipation of future chips by an order of magnitude. The possibilities for doing this are analyzed on the architectural, logical, and layout level of the implementation. It is shown that pipelining is an attractive way of parallelization enforcing localization and short critical paths which are necessary to keep the power dissipation low. Approaches to reduce the power dissipation of the clock system in high-performance chips are discussed.<<ETX>>