The creation of compact thermal models of electronic components using model reduction

This paper presents a new approach to compact thermal modeling. The paper shows how a parameterized reduced thermal model of an IC component can be created based on a parametric model reduction technique. By applying this technique, a large system of equations characterizing a discretized fully detailed numerical thermal model can be drastically reduced. The final product of a parameterized model reduction procedure is a set of small matrices presenting an abstract description of the component thermal behavior. The reduced system can be used to either synthesize a resistive network or formulate a set of connection equations to be connected to higher simulation levels. External boundary conditions are parameters of the reduced model and can be specified at simulation time. A parameterized reduced thermal model is found to have a number of advantages over an optimized resistor network model. The model can be generated quickly (one lower-upper (LU) decomposition is needed), high accuracies are obtained with a typical error of less than 0.1%. The technique also predicts temperature at all internal nodes of the original detailed model not just a single junction temperature. In this paper, the new technique is demonstrated through two examples of realistic IC components: a GaAs power amplifier and a generic multichip module ball grid array package. Both reduced models are connected to substrates in a number of different configurations. Thermal analysis performed in each case shows the importance of the geometric configuration of the connections on predictive capability.

[1]  Jia Tzer Hsu,et al.  A rational formulation of thermal circuit models for electrothermal simulation. II. Model reduction techniques [power electronic systems] , 1996 .

[2]  E.G.T. Bosch.  Thermal compact models: an alternative approach , 2003 .

[3]  M.-N. Sabry,et al.  Compact thermal models for electronic systems , 2003 .

[4]  Stephen P. Boyd,et al.  Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Michel Nakhla,et al.  Passive parameterized time-domain macromodels for high-speed transmission-line networks , 2003 .

[6]  J. D. Parry,et al.  The world of thermal characterization according to DELPHI-Part I: Background to DELPHI , 1997 .

[7]  Tom J. Smy,et al.  A 3D thermal simulation tool for integrated devices-Atar , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  J. D. Parry,et al.  The world of thermal characterization according to DELPHI-Part II: Experimental and numerical methods , 1997 .

[9]  Bart Vandevelde,et al.  A generic methodology for deriving compact dynamic thermal models, applied to the PSGA package , 1998, IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part A.

[10]  P. Maffezzoni,et al.  Analytical multipoint moment matching reduction of distributed thermal networks , 2004, IEEE Transactions on Components and Packaging Technologies.

[11]  Michel Nakhla,et al.  Multi-dimensional model reduction of VLSI interconnects , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[12]  A. Bar-Cohen,et al.  Thermal characterization of chip packages-evolutionary development of compact models , 1997, Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium.

[13]  J. DeVoe,et al.  An investigation of board level effects on compact thermal models of electronic chip packages , 2002, Eighteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium. Proceedings 2002 (Cat.No.02CH37311).

[14]  P. Stehouwer,et al.  Creation and evaluation of compact models for thermal characterisation using dedicated optimisation software , 1999, Fifteenth Annual IEEE Semiconductor Thermal Measurement and Management Symposium (Cat. No.99CH36306).

[15]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.

[16]  Rajiv V. Joshi,et al.  Simulations of local heating in VLSI backend structures using Atar , 2001 .

[17]  Marta Rencz,et al.  Dynamic thermal multiport modeling of IC packages , 2001 .

[18]  A. Bar-Cohen,et al.  Theta /sub JC/ characterization of chip packages-justification, limitations, and future , 1989, Fifth Annual IEEE Semiconductor Thermal and Temperature Measurement Symposium.

[19]  M.-N. Sabry,et al.  Dynamic Compact Thermal Models Used for Electronic Design: A Review of Recent Progress , 2003 .

[20]  Robert A. Griffin,et al.  Compact thermal models of packages used in conduction cooled applications , 2000 .

[21]  James Demmel,et al.  Applied Numerical Linear Algebra , 1997 .

[22]  Jia Tzer Hsu,et al.  A Rational Formulation of Thermal Circuit Models for Electrothermal Simulation- Part 11: Model Reduction Techniques , 1996, ISCAS 2009.

[23]  H. Vinke,et al.  Thermal characterization of electronic devices with boundary condition independent compact models , 1995 .

[24]  D. J. Walkey,et al.  Transient 3D heat flow analysis for integrated circuit devices using the transmission line matrix method on a quad tree mesh , 2001 .