An Automated Topology Synthesis Framework for Analog Integrated Circuits

This article presents an analog integrated circuit automated topology synthesis framework, where circuit topology synthesis can be efficiently realized by encoding circuit topology generation process as tree structure construction. Then the tree structures are decoded into circuit topologies. Our proposed method can not only handle large circuit designs but also generate creative topologies. To ensure only unique circuit topologies to be generated, two levels of isomorphism checks are performed at both tree structure level and circuit topology level. Then the generated un-sized circuit topologies are efficiently evaluated through a new method, which integrates topological symbolic analysis with <inline-formula> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula>/<inline-formula> <tex-math notation="LaTeX">$I_{D}$ </tex-math></inline-formula> methodology and curve-fitting technique. Along with the small-signal analysis, both linear and nonlinear programming techniques are utilized for topology feasibility checking. With only a small number of circuit topologies through the fast evaluation stage toward the subsequent detailed sizing and further evaluation, the efficiency of the whole circuit synthesis process can be significantly improved. The experimental results demonstrate high efficiency, strong reliability, and wide applicability of our proposed methods.