Digital Watermarking System using FPGA hardware for Video authentication

Abstract — This paper presents a hardware implementation of a digital watermarking system using Least Significant Bit (LSB) steganography technique in a cyclone II FPGA of the Altera family. The design utilizes the Nios embedded processor as well as specialized logic to perform the steganography steps. Experimented results show that such a hardware-based video authentication system using this watermarking technique features minimum video quality degradation and it can withstand certain potential attacks i.e. cover-up attack, cropping, segment removal on video sequences. To achieve high performance, the proposed system architecture employs pipeline structure and uses parallelism.