Warpage Suppression during FO-WLP Fabrication Process

Composing material combination of the re-distribution layer first type fan out wafer level package with various die occupancy ratio during the fabrication process on the support was studied by both of the making test vehicle and the numerical simulation. The investigated TV composed of glass support, temporary bonding adhesive, 1st re-distribution dielectric layer, Cu layer, 2nd re-distribution dielectric layer, Si die with die attached adhesive and molding compound. The fabrication was performed by the steps of applying all the materials serially and the final step of grinding down of the mold surface. The die occupation ratio in the TV become larger, the warpage of the TV decreased. The CTE of the support influenced the TV warpage significantly comparing with the CTEs of the EMC, the RDL dielectric layer and the TBA. From the investigated results the strategy of the appropriate selection of the materials to the die occupation factor was made to know. It suggested that the die occupation ratios were 21, 40 and 66%, using the support with the CTE of about 8, 10, 11 x10-6/°C and the EMC with the CTE of 8.4 x10-6/°C could make non warped TV, respectively. It was also suggested that the warpage could be controlled within 1mm during all the fabrication process steps by using the support with the CTE of 8.0 to 8.7 x10-6/°C in case of that the die occupation ratio was 40% and the CTE of EMC was 8.4 x10-6/°C.

[1]  Amy Palesko Lujan A cost analysis of RDL-first and mold-first fan-out wafer level packaging , 2016, 2016 International Conference on Electronics Packaging (ICEP).

[2]  Douglas Yu,et al.  InFO (Wafer Level Integrated Fan-Out) Technology , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[4]  Seung Wook Yoon,et al.  Thermal and electrical characterization of eWLB (embedded Wafer Level BGA) , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[5]  Chuei-Tang Wang,et al.  Signal and Power Integrity Analysis on Integrated Fan-Out PoP (InFO_PoP) Technology for Next Generation Mobile Applications , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[6]  Seung Wook Yoon,et al.  Performance & reliability characterization of eWLB (embedded wafer level BGA) packaging , 2010, 2010 12th Electronics Packaging Technology Conference.

[7]  Xuejun Fan,et al.  Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration , 2010, 2010 11th International Thermal, Mechanical & Multi-Physics Simulation, and Experiments in Microelectronics and Microsystems (EuroSimE).

[8]  Yonggang Jin,et al.  Mechanical characterization of next generation eWLB (embedded wafer level BGA) packaging , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[9]  Jerome Azemar,et al.  Fan-Out Packaging: Technologies and market trends , 2017 .

[10]  Seung Wook Yoon,et al.  3D eWLB (embedded wafer level BGA) technology for 3D-packaging/3D-SiP (Systems-in-Package) applications , 2009, 2009 11th Electronics Packaging Technology Conference.