Optimal wire retiming without binary search

The problem of retiming over a netlist of macro-blocks to achieve the minimal clock period, where the block internal structures may not be changed and flip-flops may not be inserted on some wire segments, is called the optimal wire retiming problem. To the best of our knowledge, there is no polynomial-time approach to solve it and the existence of such an approach is still an open question. We present a brand new algorithm that solves the optimal wire retiming problem with polynomial-time worst case complexity. Since the new algorithm avoids binary search and is essentially incremental, it has the potential of being combined with other optimization techniques. Experimental results show that the new algorithm is very efficient in practice.

[1]  Robert K. Brayton,et al.  Planning for performance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[2]  Robert K. Brayton,et al.  The case for retiming with explicit reset circuitry , 1996, Proceedings of International Conference on Computer Aided Design.

[3]  Evangeline F. Y. Young,et al.  Retiming with Interconnect and Gate Delay , 2003, ICCAD 2003.

[4]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.

[5]  Hai Zhou,et al.  Retiming for wire pipelining in system-on-chip , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Marios C. Papaefthymiou,et al.  DelaY: An Efficient Tool for Retiming with Realistic Delay Modeling , 1995, 32nd Design Automation Conference.

[7]  Jason Cong,et al.  Physical planning with retiming , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[8]  Martin D. F. Wong,et al.  Simultaneous routing and buffer insertion with restrictions on buffer locations , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[9]  Marios C. Papaefthymiou,et al.  Optimizing two-phase, level-clocked circuitry , 1997, JACM.

[10]  Jason Cong,et al.  Buffer block planning for interconnect-driven floorplanning , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[11]  Brian Foutz,et al.  Efficient stimulus independent timing abstraction model based on a new concept of circuit block transparency , 2002, DAC '02.

[12]  Narendra V. Shenoy,et al.  Efficient implementation of retiming , 1994, ICCAD.

[13]  Harish Kriplani,et al.  Timing model extraction of hierarchical blocks by graph reduction , 2002, DAC '02.

[14]  C. L. Liu,et al.  Optimal clock period clustering for sequential circuits with retiming , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.

[15]  Jason Cong,et al.  Incremental CAD , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[16]  Ganesh Gopalakrishnan,et al.  Performance analysis and optimization of asynchronous circuits , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[17]  Cheng-Kok Koh,et al.  Interconnect Planning with Local Area Constrained Retiming , 2003 .

[18]  Soha Hassoun,et al.  Optimal path routing in single- and multiple-clock domain systems , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Evangeline F. Y. Young,et al.  Performance-driven register insertion in placement , 2004, ISPD '04.

[20]  Hai Zhou,et al.  Wire retiming for system-on-chip by fixpoint computation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[21]  Hai Zhou,et al.  Simultaneous routing and buffer insertion with restrictions on buffer locations , 1999, DAC '99.

[22]  Leon Stok,et al.  Retiming revisited and reversed , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Cheng-Kok Koh,et al.  Flip-flop and repeater insertion for early interconnect planning , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[24]  Hai Zhou.  Deriving a new efficient algorithm for min-period retiming , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[25]  Sandy Irani,et al.  Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems , 1999, DAC '99.

[26]  Pasquale Cocchini.  Concurrent flip-flop and repeater insertion for high performance integrated circuits , 2002, ICCAD 2002.

[27]  Eby G. Friedman,et al.  Incorporating interconnect, register, and clock distribution delays into the retiming process , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Ajay J. Daga,et al.  Automated timing model generation , 2002, DAC '02.

[29]  Nataraj Akkiraju,et al.  Spec based flip-flop and buffer insertion , 2003, Proceedings 21st International Conference on Computer Design.

[30]  Sachin S. Sapatnekar,et al.  A fresh look at retiming via clock skew optimization , 1995, DAC '95.

[31]  Miodrag Potkonjak,et al.  Performance optimization of sequential circuits by eliminating retiming bottlenecks , 1992, ICCAD.

[32]  S. Shekhar,et al.  Multilevel Hypergraph Partitioning: Application In Vlsi Domain , 1997, Proceedings of the 34th Design Automation Conference.