Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking

This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is obtained by taking two 1-dimensional DCTs in series. The image pixel value is first divided into 8x8 blocks and the row-wise 1D DCT of each block is taken. The transpose of the blocks is then determined and a column-wise 1D DCT is ascertained which gives the 2D DCT of the data. The major advantage of this design is that, unlike the conventional DCT-based watermarking technique, this method uses a 5-stage pipeline which can bring about a speed increase of close to 500% over the conventional method which is naturally a great advantage. This technique has been tested on the standard ‘Lena’ image. Both visible and invisible watermarking is implemented in hardware. The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b. Matlab is used to produce the binary data file which is the input to the 1D DCT module. The hardware implementation is done in Xilinx XC3S4000 FPGA. The results of the comparison are discussed in the concluding sections.

[1]  S.A. Kasmani,et al.  A New Robust Digital Image Watermarking Technique Based on Joint DWT-DCT Transformation , 2008, 2008 Third International Conference on Convergence and Hybrid Information Technology.

[2]  M. Morris Mano,et al.  Computer system architecture , 1982 .

[3]  Stamatis Vassiliadis,et al.  DCT and IDCT Implementations on Different FPGA Technologies , 2022 .

[4]  Amar Aggoun,et al.  Two-dimensional DCT/IDCT architecture , 2003 .

[5]  R. F. Woods,et al.  IMPLEMENTATION OF THE 2 D DCT USING A XILINX XC 6264 FPGA , 1998 .

[6]  Magdy A. Bayoumi,et al.  Area-Efficient NEDA Architecture for The 1-D DCT/IDCT , 2006, 2006 IEEE International Conference on Acoustics Speech and Signal Processing Proceedings.

[7]  Magdy Bayoumi,et al.  Implementation of NEDA-based DCT architecture using even-odd decomposition of the 8 × 8 DCT matrix , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[8]  Chunyan Wang,et al.  Recursive algorithm, architectures and FPGA implementation of the two-dimensional discrete cosine transform , 2008 .

[9]  G.S. Moschytz,et al.  Practical fast 1-D DCT algorithms with 11 multiplications , 1989, International Conference on Acoustics, Speech, and Signal Processing,.

[10]  Roger Woods,et al.  Implementation of the 2D DCT using a Xilinx XC6264 FPGA , 1997, 1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation formerly VLSI Signal Processing.

[11]  Kuo-Hsing Cheng,et al.  The design and implementation of DCT/IDCT chip with novel architecture , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[12]  Tughrul Arslan,et al.  Low power DCT implementation approach for VLSI DSP processors , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).