Spintronic Processing Unit Within Voltage-Gated Spin Hall Effect MRAMs

Realization of the unity of processing and storage in the same chip/die has initialized a promising research direction of processing-in-memory (PIM), attempting to address the “memory wall” challenge in typical von-Neumann computing architectures. Nevertheless, there still exist many issues, which require an efficient implementation of PIM. In this paper, we propose a novel PIM paradigm and architecture to support a spintronic processing unit (SPU), within voltage-gated spin Hall effect driven MRAMs. Different from previous studies, the data initially stored in the memory units are treated as logic input operands and the logic output results are in situ stored in the memory units themselves. More importantly, the proposed SPU works just like a typical memory, and all the logic functions are achieved through regular memory-like read/write operations. Besides, a 1-b full adder based on different array structures (including typical array and crossbar array) is implemented and the possibility of block parallel is discussed. Furthermore, we propose a novel reconfigure architecture, which efficiently translates logical tasks into concrete regular memory-like read/write operations, to support the SPU. Under the 40 nm process technology node, the proposed 1-b full adder can achieve ∼20.00 ns/b (∼8.33 ns/b) and ∼63.8 fJ/b (∼77.35 fJ/b) based on the typical array (crossbar array) structure.

[1]  Jian-Ping Wang,et al.  A spintronics full adder for magnetic CPU , 2005 .

[2]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[3]  Wei-gang Wang,et al.  Electric-field-assisted switching in magnetic tunnel junctions. , 2012, Nature materials.

[4]  U. Böttger,et al.  Beyond von Neumann—logic operations in passive crossbar arrays alongside memory operations , 2012, Nanotechnology.

[5]  J. G. Alzate,et al.  Voltage-induced switching of nanoscale magnetic tunnel junctions , 2012, 2012 International Electron Devices Meeting.

[6]  Yuan Xie.  Future memory and interconnect technologies , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[7]  Uri C. Weiser,et al.  Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Daisuke Suzuki,et al.  Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  Kiyoung Choi,et al.  PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture , 2015, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA).

[10]  C. Chappert,et al.  A study of perpendicular-anisotropy magnetic tunnel junction switched by spin-Hall-assisted spin-transfer torque , 2015, 2015 IEEE Magnetics Conference (INTERMAG).

[11]  Stratos Idreos,et al.  JAFAR: Near-Data Processing for Databases , 2015, SIGMOD Conference.

[12]  Mahdi Jamali,et al.  Spin Analog-to-Digital Convertor Using Magnetic Tunnel Junction and Spin Hall Effect , 2015, IEEE Electron Device Letters.

[13]  Rajiv V. Joshi,et al.  An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

[14]  Zhaohao Wang,et al.  Spintronic logic design methodology based on spin Hall effect–driven magnetic tunnel junctions , 2016, Journal of Physics D: Applied Physics.

[15]  Giovanni De Micheli,et al.  The Programmable Logic-in-Memory (PLiM) computer , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[16]  B. Koopmans,et al.  Field-free magnetization reversal by spin-Hall effect and exchange bias , 2015, Nature Communications.

[17]  Lifeng Liu,et al.  Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large‐Scale Circuits , 2016, Advanced materials.

[18]  Hao Yu,et al.  Non-Volatile In-Memory Computing by Spintronics , 2016, Non-Volatile In-Memory Computing by Spintronics.

[19]  M. Shimizu,et al.  Voltage-control spintronics memory (VoCSM) having potentials of ultra-low energy-consumption and high-density , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[20]  Kaushik Roy,et al.  Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing , 2014, IEEE Transactions on Neural Networks and Learning Systems.

[21]  Taejoong Song,et al.  28-nm 1T-1MTJ 8Mb 64 I/O STT-MRAM with symmetric 3-section reference structure and cross-coupled sensing amplifier , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[22]  Weisheng Zhao,et al.  Modeling and Exploration of the Voltage-Controlled Magnetic Anisotropy Effect for the Next-Generation Low-Power and High-Speed MRAM Applications , 2017, IEEE Transactions on Nanotechnology.

[23]  Rolf Drechsler,et al.  A PLiM Computer for the Internet of Things , 2017, Computer.

[24]  Weisheng Zhao,et al.  Large voltage-controlled magnetic anisotropy in the SrTiO3/Fe/Cu structure , 2017 .

[25]  Ronald F. DeMara,et al.  Energy-Efficient and Process-Variation-Resilient Write Circuit Schemes for Spin Hall Effect MRAM Device , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[26]  Gert Cauwenberghs,et al.  Memristor for computing: Myth or reality? , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[27]  Lirida A. B. Naviner,et al.  Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[28]  Weifeng Lv,et al.  Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM , 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

[29]  N. Shimomura,et al.  Voltage-Control Spintronics Memory With a Self-Aligned Heavy-Metal Electrode , 2017, IEEE Transactions on Magnetics.

[30]  He Zhang,et al.  Stateful Reconfigurable Logic via a Single-Voltage-Gated Spin Hall-Effect Driven Magnetic Tunnel Junction in a Spintronic Memory , 2017, IEEE Transactions on Electron Devices.

[31]  Shinobu Fujita,et al.  High-Speed Voltage-Control Spintronics Memory (High-Speed VoCSM) , 2017, 2017 IEEE International Memory Workshop (IMW).

[32]  K. L. Wang,et al.  Analog to Stochastic Bit Stream Converter Utilizing Voltage-Assisted Spin Hall Effect , 2017, IEEE Electron Device Letters.

[33]  Zhaohao Wang,et al.  High-Density NAND-Like Spin Transfer Torque Memory With Spin Orbit Torque Erase Operation , 2018, IEEE Electron Device Letters.

[34]  Rolf Drechsler,et al.  Logic Synthesis for RRAM-Based In-Memory Computing , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[35]  Anand Raghunathan,et al.  Computing in Memory With Spin-Transfer Torque Magnetic RAM , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[36]  Zhaohao Wang,et al.  Field-Free Switching of Perpendicular Magnetic Tunnel Junction via Voltage-Gated Spin Hall Effect for Low-Power Spintronic Memory , 2018, 1804.11025.

[37]  A. Fert,et al.  Current-induced magnetization switching in atom-thick tungsten engineered perpendicular magnetic tunnel junctions with large tunnel magnetoresistance , 2017, Nature Communications.

[38]  Sachin S. Sapatnekar,et al.  Efficient In-Memory Processing Using Spintronics , 2018, IEEE Computer Architecture Letters.

[39]  Yang Liu,et al.  Field-free Magnetization Switching by Utilizing the Spin Hall Effect and Interlayer Exchange Coupling of Iridium , 2018, Scientific Reports.

[40]  Sarjoosing Goolaup,et al.  Field-free spin-orbit torque switching of a perpendicular ferromagnet with Dzyaloshinskii-Moriya interaction , 2019, Applied Physics Letters.