A 1.5-V 12-bit power-efficient continuous-time third-order /spl Sigma//spl Delta/ modulator

This paper presents the design strategy, implementation, and experimental results of a power-efficient third-order low-pass /spl Sigma//spl Delta/ analog-to-digital converter (ADC) using a continuous-time (CT) loop filter. The loop filter has been implemented by using active RC integrators. Several power optimizations, design requirements, and performance limitations relating to circuit nonidealities in the CT modulator are presented. The influence of the low supply voltage on the various building blocks such as the amplifier as well as on the overall /spl Sigma//spl Delta/ modulator is discussed. The ADC was implemented in a 3.3-V 0.5-/spl mu/m CMOS technology with standard threshold voltages. Measurements of the low-power 1.5-V CT /spl Sigma//spl Delta/ ADC show a dynamic range and peak signal-to-noise-plus-distortion ratio of 80 and 70 dB, respectively, in a bandwidth of 25 kHz. The measured power consumption is only 135 /spl mu/W from a single 1.5-V power supply.

[1]  G. Burbach,et al.  Trimless high precision ratioed resistors in D/A and A/D converters , 1995 .

[2]  Friedel Gerfers,et al.  A design strategy for low-voltage low-power continuous-time /spl Sigma//spl Delta/ A/D converters , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[3]  Maurits Ortmanns,et al.  Figure of merit based design strategy for low-power continuous-time /spl Sigma//spl Delta/ modulators , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[4]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[5]  W. Sansen,et al.  A 900-mV low-power ΔΣ A/D converter with 77-dB dynamic range , 1998, IEEE J. Solid State Circuits.

[6]  G. Fischer,et al.  Alternative topologies for sigma-delta modulators-a comparative study , 1997 .

[7]  Mohammed Ismail,et al.  A 2.7-V elliptical MOSFET-only g/sub m/C-OTA filter , 2000 .

[8]  Michel Steyaert,et al.  Optimal parameters for /spl Delta//spl Sigma/ modulator topologies , 1998 .

[9]  F. Henkel,et al.  A 1 MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[10]  H. Tao,et al.  Analysis of timing jitter in bandpass sigma-delta modulators , 1999 .

[11]  Michel Steyaert,et al.  Custom analog low power design: the problem of low voltage and mismatch , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[12]  E.J. van der Zwan,et al.  A 0.2 mW CMOS /spl Sigma//spl Delta/ modulator for speech coding with 80 dB dynamic range , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.