High-Level Design and Validation of the

[1]  Flavius Gruian,et al.  VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture , 2008, SAC '08.

[2]  Madan Musuvathi,et al.  Iterative context bounding for systematic testing of multithreaded programs , 2007, PLDI '07.

[3]  Min Xu,et al.  A regulated transitive reduction (RTR) for longer memory race recording , 2006, ASPLOS XII.

[4]  J. Gregory Steffan,et al.  The microarchitecture of FPGA-based soft processors , 2005, CASES '05.

[5]  John Wawrzynek,et al.  BEE2: a high-end reconfigurable computing system , 2005, IEEE Design & Test of Computers.

[6]  Nirav Hemant Dave.  Designing a Processor in Bluespec , 2005 .

[7]  Roland E. Wunderlich,et al.  In-system FPGA prototyping of an Itanium microarchitecture , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[8]  Rainer Leupers,et al.  RTL processor synthesis for architecture exploration and implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[9]  Fredrik Larsson,et al.  Simics: A Full System Simulation Platform , 2002, Computer.

[10]  Yoshinori Takeuchi,et al.  PEAS-III: an ASIP design environment , 2000, Proceedings 2000 International Conference on Computer Design.

[11]  Daniel D. Gajski,et al.  SPECC: Specification Language and Methodology , 2000 .

[12]  Burton J. Smith.  Architecture And Applications Of The HEP Multiprocessor Computer System , 1982, Optics & Photonics.