Semi-analytical modelling of short channel effects in Si double gate, tri-gate and gate all-around MOSFETs

An analytical expression for the three-dimensional potential distribution along the channel of short channel silicon multi-gate MOSFETs is described in weak inversion. The analytical solutions cover three different cases of multi-gate devices: Symmetrical double gate (DG), tri-gate (TG) and gate-all-around (GAA) MOSFETs. Using the three-dimensional potential distribution in the silicon film, the subthreshold drain current is calculated from which the threshold voltage and the subthreshold swing were extracted. The threshold voltage roll-off, the subthreshold swing and the drain-induced barrier lowering of the multi-gate devices are compared, showing the critical advantage of GAA structures concerning the short channel effects. (© 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

[1]  Jean-Pierre Colinge,et al.  Multiple-gate SOI MOSFETs , 2004 .

[2]  T. Sugii,et al.  Analytical threshold voltage model for short channel double-gate SOI MOSFETs , 1996 .

[3]  G. Ghibaudo,et al.  Semi-Analytical Modeling of Short-Channel Effects in Si and Ge Symmetrical Double-Gate MOSFETs , 2007, IEEE Transactions on Electron Devices.

[4]  T. Sugii,et al.  Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's , 1994, IEEE Electron Device Letters.

[5]  Te-Kuang Chiang A novel scaling-parameter-dependent subthreshold swing model for double-gate (DG) SOI MOSFETs: including effective conducting path effect (ECPE) , 2004 .

[6]  E. Harrell,et al.  A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs , 2003 .

[7]  G. Katti,et al.  Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation , 2006, IEEE Transactions on Electron Devices.

[8]  Hiroki Nakamura,et al.  Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering , 2006, IEICE Trans. Electron..

[9]  Yuan Taur,et al.  A 2-D analytical solution for SCEs in DG MOSFETs , 2004 .

[10]  Yuan Taur,et al.  Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs , 2001 .

[11]  G. Pei,et al.  FinFET design considerations based on 3-D simulation and analytical modeling , 2002 .

[12]  A. DasGupta,et al.  Threshold Voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation , 2004, IEEE Transactions on Electron Devices.

[13]  Jin-Hau Kuo,et al.  Deep submicrometer double-gate fully-depleted SOI PMOS devices: a concise short-channel effect threshold voltage model using a quasi-2D approach , 1996 .

[14]  K. F. Lee,et al.  Scaling the Si MOSFET: from bulk to SOI to bulk , 1992 .