A 0.94-ps-RMS-jitter 0.016-mm/sup 2/ 2.5-GHz multiphase generator PLL with 360/spl deg/ digitally programmable phase shift for 10-Gb/s serial links

A novel architecture for clock generation in dual-loop subrate clock and data recovery (CDR) circuits is proposed based on an adjustable phase-locked loop (PLL). The adjustable PLL (adjPLL) generates eight equidistant clock phases, whose timing with respect to a reference clock can be simultaneously shifted in steps of 3 ps, controllable by a digital value. The programmable phase shift is achieved by adding the weighted outputs of several XOR phase detectors. The measured tracking jitter of the PLL, fabricated in 90-nm SOI CMOS, is 0.94 ps rms at 2.5 GHz, and the power consumption is 20 mW at V/sub DD/=0.9 V. The circuit occupies an area of only 0.016 mm/sup 2/.

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