Comparison of the chip area usage of 2-level and 3-level voltage source converter topologies

In the low voltage converter range, 3-phase 3-level VSC topologies are not wide spread in industry because of the increased part count and higher costs, although they are more efficient for higher switching frequencies. In this paper an alternative 3-level topology referred to as T-type is presented, which is very high efficient for medium switching frequencies (4–20 kHz). Additionally, it is shown that the total silicon chip area of a 3-level topology can be lower than in a 2-level topology since the losses are distributed over more components leading to only a small increase in the junction temperature. This allows for the design of a chip area and cost optimized 3-level bridge leg module for the mass market.

[1]  Qi Wei,et al.  Analytical calculation of the average and RMS currents in three-level NPC inverter with SPWM , 2009 .

[2]  T. Friedli,et al.  A Semiconductor Area Based Assessment of AC Motor Drive Converter Topologies , 2009, 2009 Twenty-Fourth Annual IEEE Applied Power Electronics Conference and Exposition.

[3]  I. Rasoanarivo,et al.  A new multilevel inverter model NP without clamping diodes , 2008, 2008 34th Annual Conference of IEEE Industrial Electronics.

[4]  S. Bernet,et al.  A comparison of three-level converters versus two-level converters for low-voltage drives, traction, and utility applications , 2005, IEEE Transactions on Industry Applications.

[5]  Wei Xu,et al.  Speed sensorless direct torque control of 3-level inverter-fed induction motor drive based on optimized switching table , 2009, 2009 35th Annual Conference of IEEE Industrial Electronics.

[6]  Marco Liserre,et al.  The high efficiency transformer-less PV inverter topologies derived from NPC topology , 2009, 2009 13th European Conference on Power Electronics and Applications.

[7]  Nobuyuki Matsui,et al.  PWM control and input characteristics of three-phase multi-level AC/DC converter , 1992, PESC '92 Record. 23rd Annual IEEE Power Electronics Specialists Conference.

[8]  D. Floricau,et al.  New three level topology with shared components: Properties, losses, and control strategy , 2009, 2009 35th Annual Conference of IEEE Industrial Electronics.

[9]  M. Schweizer,et al.  Comparison and implementation of a 3-level NPC voltage link back-to-back converter with SiC and Si diodes , 2010, 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC).

[10]  B. Fuld.  Aufwandsarmer Thyristor-Dreistufen-Wechsebrichter mit geringen Verlusten , 1989 .

[11]  Satoru Sone,et al.  Switching loss minimised space vector PWM method for IGBT three-level inverter , 1997 .

[12]  Dong-Seok Hyun,et al.  Study of neutral point potential variation for three-level NPC inverter under fault condition , 2008, 2008 34th Annual Conference of IEEE Industrial Electronics.