FFT-based calibration method for 1.5 bit/stage pipelined ADCs

A fast Fourier transform FFT-based digital calibration method for 1.5 bit/stage pipeline analog-to-digital converter ADC is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier OPAMP can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non-ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low-gain OPAMP can be used in high-performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal-to-noise-and-distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley & Sons, Ltd.

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