Single step current driven routing of multiterminal signal nets for analog applications

We present the single layer router CDR (Current Driven Router) capable of routing analog multiterminal signal nets with current driven wire widths. The widths used during routing are determined by current properties per terminal gained by simulation or manually specified by circuit designers. The algorithm presented computes a Steiner tree layout satisfying all specified current constraints while obeying the maximum allowed current densities on all connections. CDR calculates the Steiner tree topology, computes the unknown currents of wires connecting two Steiner points and generates the final Steiner tree layout in a single step thus eliminating the need for a separate layout post-processing step common to power and ground routing algorithms. CDR uses a connection graph for layout representation and applies an advanced minimum detour algorithm in combination with a modified 'three-point steinerization' heuristic for Steiner tree based layout construction.

[1]  D. T. Lee,et al.  Rectilinear shortest paths with rectangular barriers , 1985, SCG '85.

[2]  R. Prim Shortest connection networks and some generalizations , 1957 .

[3]  Edsger W. Dijkstra,et al.  A note on two problems in connexion with graphs , 1959, Numerische Mathematik.

[4]  S. Sitharama Iyengar,et al.  Finding obstacle-avoiding shortest paths using implicit connection graphs , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  C. Y. Lee An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[6]  Majid Sarrafzadeh,et al.  An Introduction To VLSI Physical Design , 1996 .

[7]  J. S. Lee,et al.  Use of steiner's problem in suboptimal routing in rectilinear metric , 1976 .

[8]  F. Hwang On Steiner Minimal Trees with Rectilinear Distance , 1976 .

[9]  Chak-Kuen Wong,et al.  Rectilinear Shortest Paths and Minimum Spanning Trees in the Presence of Rectilinear Obstacles , 1987, IEEE Transactions on Computers.

[10]  Kinya Tabuchi,et al.  A computer program for optimal routing of printed circuit conductors , 1968, IFIP Congress.

[11]  Kenneth L. Clarkson,et al.  Rectilinear shortest paths through polygonal obstacles in O(n(logn)2) time , 1987, SCG '87.

[12]  Hans Jürgen Prömel,et al.  The Steiner Tree Problem , 2002 .

[13]  Dieter A. Mlynski,et al.  Computation of Power Supply Nets in VLSI Layout , 1981, 18th Design Automation Conference.

[14]  Nils J. Nilsson,et al.  A Formal Basis for the Heuristic Determination of Minimum Cost Paths , 1968, IEEE Trans. Syst. Sci. Cybern..

[15]  Sheldon B. Akers,et al.  A Modification of Lee's Path Connection Algorithm , 1967, IEEE Trans. Electron. Comput..

[16]  D. Hightower,et al.  A solution to line routing problems on the continuous plane , 1988 .

[17]  Frank O. Hadlock,et al.  A shortest path algorithm for grid graphs , 1977, Networks.

[18]  M. Hanan,et al.  On Steiner’s Problem with Rectilinear Distance , 1966 .

[19]  Jiri Soukup,et al.  Fast Maze Router , 1978, 15th Design Automation Conference.

[20]  Dieter A. Mlynski,et al.  Automatic Variable-Width Routing for VLSI , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  David S. Johnson,et al.  The Rectilinear Steiner Tree Problem is NP Complete , 1977, SIAM Journal of Applied Mathematics.

[22]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[23]  S. Chowdhury An Automated Design of Minimum-Area IC Power/Ground Nets , 1987, 24th ACM/IEEE Design Automation Conference.

[24]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.