Centralized Adaptive Routing for NoCs
暂无分享,去创建一个
Avinoam Kolodny | Israel Cidon | Ran Manevich | Isask'har Walter | Ran Manevich | I. Cidon | A. Kolodny | I. Walter
[1] Leslie G. Valiant,et al. Universal schemes for parallel communication , 1981, STOC '81.
[2] P. R. Bell,et al. Review of point-to-point network routing algorithms , 1986, IEEE Communications Magazine.
[3] Gregory G. Finn,et al. Routing and Addressing Problems in Large Metropolitan-Scale Internetworks. ISI Research Report. , 1987 .
[4] William J. Dally,et al. Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels , 1993, IEEE Trans. Parallel Distributed Syst..
[5] José Duato,et al. A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks , 1993, IEEE Trans. Parallel Distributed Syst..
[6] S. Lennart Johnsson,et al. ROMM routing on mesh and torus networks , 1995, SPAA '95.
[7] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.
[8] The Turn Model for Adaptive Routing , 1998, 25 Years ISCA: Retrospectives and Reprints.
[9] Ge-Ming Chiu,et al. The Odd-Even Turn Model for Adaptive Routing , 2000, IEEE Trans. Parallel Distributed Syst..
[10] Fredrik Larsson,et al. Simics: A Full System Simulation Platform , 2002, Computer.
[11] William J. Dally,et al. GOAL: a load-balanced adaptive routing algorithm for torus networks , 2003, ISCA '03.
[12] L. Benini,et al. Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.
[13] Fernando Gehm Moraes,et al. HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..
[14] William J. Dally,et al. Globally Adaptive Load-Balanced Routing on Tori , 2004, IEEE Computer Architecture Letters.
[15] Radu Marculescu,et al. DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..
[16] Ran Ginosar,et al. QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..
[17] Kees Goossens,et al. AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.
[18] DaeHo Seo,et al. Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks , 2005, ISCA 2005.
[19] Ming Li,et al. DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[20] Ran Ginosar,et al. The Power of Priority: NoC Based Distributed Cache Coherency , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[21] Idit Keidar,et al. NoC-Based FPGA: Architecture and Routing , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[22] Stephen W. Keckler,et al. Regional congestion awareness for load balance in networks-on-chip , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.
[23] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[24] Avinoam Kolodny,et al. Best of both worlds: A bus enhanced NoC (BENoC) , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[25] Hamid Sarbazi-Azad,et al. A Load-Balanced Routing Scheme for NoC-Based Systems-on-Chip , 2010, 2010 First Workshop on Hardware and Software Implementation and Control of Distributed MEMS.
[26] Bill Lin,et al. Destination-based adaptive routing on 2D mesh networks , 2010, 2010 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS).
[27] Fernando Gehm Moraes,et al. Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip , 2010, SBCCI '10.
[28] B. Hoefflinger. ITRS: The International Technology Roadmap for Semiconductors , 2011 .