A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications

The integration of the power amplifier (PA) is one of the greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PA's in CMOS [1–4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-to-average ratio (PAR) and therefore requires a highly linear PA. In addition, WLAN SoCs are evolving to accommodate more advanced applications, like the transmission and reception of multiple streams of high-definition video across long distances. This requires a higher linear transmit power. However, the low power supply, lossy substrate and lower breakdown voltage make the design of a linear, high power, high efficiency and reliable CMOS PA quite challenging. In this paper, a linear 65nm CMOS PA operating at 3.3V supply with an on-chip distributed LC power combining network and improved linearization is presented. The result is the highest combination of output power and efficiency yet reported for a packaged linear WLAN amplifier at 2.4GHz in a CMOS process.

[1]  Ali M. Niknejad,et al.  A single-chip highly linear 2.4GHz 30dBm power amplifier in 90nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Qiang Li,et al.  A Fully Integrated MIMO Multiband Direct Conversion CMOS Transceiver for WLAN Applications (802.11n) , 2007, IEEE Journal of Solid-State Circuits.

[3]  A. Scuderi,et al.  A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control , 2009, IEEE Journal of Solid-State Circuits.

[4]  L.E. Larson,et al.  A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers , 2004, IEEE Journal of Solid-State Circuits.

[5]  Lawrence E. Larson,et al.  Fully integrated dual-band power amplifiers with on-chip baluns in 65nm CMOS for an 802.11n MIMO WLAN SoC , 2009, 2009 IEEE Radio Frequency Integrated Circuits Symposium.

[6]  Ali M. Niknejad,et al.  Current combining 60GHz CMOS power amplifiers , 2009, 2009 IEEE Radio Frequency Integrated Circuits Symposium.

[7]  David Ruffieux,et al.  A 1V RF SoC with an 863-to-928MHz 400kb/s radio and a 32b Dual-MAC DSP core for Wireless Sensor and Body Networks , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[8]  Ali Hajimiri,et al.  A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier , 2008, IEEE Journal of Solid-State Circuits.