Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement
暂无分享,去创建一个
In this paper, we present a dynamically reconfigurable multi-context FPGA named Flexible Processor (FP) equipped with shift-register temporal communication module (SR-TCM). Temporal partitioning algorithm has been developed, which divides a long critical path into equal-length short paths context-wise. From measurement results of a FP fabricated by using a 90nm CMOS technology, it is found that the execution latency remains constant regardless of the number of contexts used.
[1] Tadahiro Ohmi,et al. Delay evaluation of 90nm CMOS multi-context FPGA with shift-register-type temporal communication module for large-scale circuit emulation , 2008, 2008 International Conference on Field-Programmable Technology.
[2] Malgorzata Marek-Sadowska,et al. Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs , 1999, IEEE Trans. Computers.
[3] N. Miyamoto,et al. A Personal-Use Single-Chip Emulator Using Dynamically Reconfigurable Logic Array , 2005, 2005 IEEE Asian Solid-State Circuits Conference.