An 18 V Input 10 MHz Buck Converter With 125 ps Mixed-Signal Dead Time Control
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Bernhard Wicht | Juergen Wittmann | Thoralf Rosahl | Alexander Barner | B. Wicht | J. Wittmann | Thoralf Rosahl | A. Barner
[1] Amit Patra,et al. Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications , 2011, 2011 24th Internatioal Conference on VLSI Design.
[2] H. Benda,et al. Reverse recovery processes in silicon power rectifiers , 1967 .
[3] A. Tuszynski,et al. CMOS tapered buffer , 1990 .
[4] Bernhard Wicht,et al. A 12V 10MHz buck converter with dead time control based on a 125 ps differential delay chain , 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).
[5] N. Takai,et al. Sawtooth generator using two triangular waves , 2008, 2008 51st Midwest Symposium on Circuits and Systems.
[6] Mircea R. Stan,et al. Split-path skewed (SPS) CMOS buffer for high performance and low power applications , 2001 .
[7] Bernhard Wicht,et al. MHz-converter design for high conversion ratio , 2013, 2013 25th International Symposium on Power Semiconductor Devices & IC's (ISPSD).
[8] I. Batarseh,et al. Maximum Efficiency Point Tracking (MEPT) Method and Digital Dead Time Control Implementation , 2006, IEEE Transactions on Power Electronics.
[9] Chern-Lin Chen,et al. Zero-Voltage-Switching Control for a PWM Buck Converter Under DCM/CCM Boundary , 2009, IEEE Transactions on Power Electronics.
[10] Wei Li,et al. Dynamic dead-time controller for synchronous buck DC-DC converters , 2010 .
[11] Bernhard Wicht,et al. A configurable sawtooth based PWM generator with 2 ns on-time for >50 MHz DCDC converters , 2015, 2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).
[12] Philip K. T. Mok,et al. Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation , 2010, IEEE Journal of Solid-State Circuits.
[13] Bram Nauta,et al. Design and Analysis of a High-Efficiency High-Voltage Class-D Power Output Stage , 2014, IEEE Journal of Solid-State Circuits.
[14] Torsten Lehmann,et al. Nanosecond Delay Floating High Voltage Level Shifters in a 0.35 $\mu$m HV-CMOS Technology , 2011, IEEE Journal of Solid-State Circuits.
[15] S. Mapus. Predictive gate drive boosts synchronous dcidc power converter efficiency , 2003 .
[16] Jinseok Park,et al. Switching losses analysis in MHz integrated synchronous Buck converter to support optimal power stage width segmentation in CMOS technology , 2010, 2010 IEEE Energy Conversion Congress and Exposition.
[17] Cheng Huang,et al. An 84.7% Efficiency 100-MHz Package Bondwire-Based Fully Integrated Buck Converter With Precise DCM Operation and Enhanced Light-Load Efficiency , 2013, IEEE Journal of Solid-State Circuits.
[18] Bernhard Wicht,et al. A 50V high-speed level shifter with high dv/dt immunity for multi-MHz DCDC converters , 2014, ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC).
[19] M. Berkhout. A class D output stage with zero dead time , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[20] Jader A. De Lima,et al. A gm-C Ramp Generator for Voltage Feedforward Control of DC-DC Switching Regulators , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[21] Wolfgang Pribyl,et al. Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOS , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).