First-Order Digital Phase Lock Loop with Continuous Locking

A zero-crossing digital phase locked loop (ZCDPLL) system with dual gain selection technique for fast acquisition, reliable locking and improved phase noise and jitter performance is proposed. The system is designed and simulated based on adaptive loop gain techniques. It utilizes the wide locking range properties and fast acquisition of the high gain loop and enhanced noise performance of the low gain loop. The simulation results confirmed the new system's ability to switch between high and low gain loops in order to acquire fast acquisition, while keeping the loop in lock. In this approach the system will maintain the desired properties of fast acquisition and wide locking. These characteristics are normally in conflict with each other. The noise performance of the system has been tested and shown to give improved jitter and phase noise which makes the loop very attractive frequency synthesis and other communications and control applications.

[2]  Saleh R. Al-Araji,et al.  Digital Phase Lock Loops: Architectures and Applications , 2006 .

[3]  Jérôme Juillard,et al.  Synchronization Analysis of Networks of Self-Sampled All-Digital Phase-Locked Loops , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  B. Cernuschi-Frias,et al.  An extension of the Gill and Gupta discrete phase-locked loop , 1980, Proceedings of the IEEE.

[5]  Floyd M. Gardner,et al.  Phaselock techniques , 1984, IEEE Transactions on Systems, Man, and Cybernetics.

[6]  K. Kishine,et al.  Fast-acquisition PLL using fully digital natural-frequency-switching technique , 2008 .

[7]  Saleh R. Al-Araji,et al.  Digital Phase Lock Loops , 2006 .

[8]  Floyd M. Gardner,et al.  Phaselock Techniques: Gardner/Phaselock Techniques , 2005 .

[9]  Saleh R. Al-Araji,et al.  Performance evaluation of Sigma Delta Zero Crossing DPLL , 2011, 2011 18th IEEE International Conference on Electronics, Circuits, and Systems.

[10]  Saleh R. Al-Araji,et al.  Rapid acquisition adaptive zero-crossing DPLL , 2005, SPIE Micro + Nano Materials, Devices, and Applications.

[11]  Q. Nasir,et al.  Enhanced performance Zero Crossing DPLL with linearized phase detector , 2008, 2008 International Symposium on Telecommunications.