Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits

Test response compaction offers test time and data volume reduction on the output side. An on-chip circuitry, denoted as the response compactor, is utilized, compressing the responses of the circuit, and thus enabling the storage of compacted responses on the tester memory. While the test cost is thus reduced, such a circuitry may result in error masking, and hence the degradation of the fault/error coverage level. Response bits that are unknown during simulation time pose additional challenges on the design of a response compactor, as they contribute to error masking also. Assumptions regarding a particular fault model and/or distribution of unknown response bits ease the design of a response compactor; however, the coverage loss of unmodeled faults is inevitable in the presence of such a compactor. Furthermore, modeled faults also may become unobserved if the distribution of unknown bits deviates from the assumed one. In this paper, we propose a response compaction technique that is independent of any fault model. We design the response compactor based on the expected responses of the circuit under test. As a result, any originally detectable unmodeled defect or modeled fault is still detectable with the proposed compactor, regardless of the number and the distribution of the unknown response bits. The output bit-width of the proposed response compactor is also the minimum that can be achieved when original defect and fault coverage levels are delivered. We also present an analysis that can be utilized for a quick computation of parameters, such as the lower and upper bounds and the expected value for the optimal output bandwidth, which the proposed compaction methodology is capable of attaining. As the proposed technique is a test set-dependent approach, it is more suitable for application in the domain of core-based system-on-chips (SOCs), wherein a set of test vectors and expected responses is delivered along with a core. Parallelism among core tests is increased by narrowing down the bit-width for each core, delivering test time reduction for the SOCs.

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