Automated RTL generator

Code generation is a vast topic and has been discussed and implemented for quite a while now. It has been also been a topic of debate as to what is an ideal code generator and how an ideal code generator can be created. The biggest challenge while creating a code generator is to maintain a balance between the amount of freedom given to the user and the restrictions imposed on the code generated. These two seemed to be very conflicting requirements while designing the Automated RTL Code Generator. If the code generator tries to be rigid and sticks to well-defined paths and restricted code, the flexibility provided to the also reduces. It is a very interesting task to strike the right amount of balance and generate code of high quality and well-defined standards. Verilog code is a type of RTL (Register Transfer Level) that itself has fewer constructs and variety as compared to pure software languages like Java, or Python so it makes sense to generate it automatically so that the hardware designers are relieved from the mundane tasks of writing repetitive verilog code modules. Also code generator provides a nice introduction to the much wider topic of compiler design. This project also tries to delve deeper into the latest IPXACT XML standard IEEE 1865-2009 which is used for hardware description and will provide means of generating verilog code directly from it. ACKNOWLEDGMENTS I would like to thank my project advisor, Dr. Robert Chun, for his guidance, encouragement and unwavering faith in my project. He was completely supportive despite the fact that I was working on a hardware domain based project, which was a new domain for me. I would also like to thank my committee members: Dr. Soon Tee Teoh and for his feedback and suggestions and Kristopher Bechamp for introducing me to the domain while at Xilinx Inc. Finally I would like to thank my family who have always been with me through whatever I have set out to achieve. Table of