Abstracting Modern FCCMs To Provide a Single Interface to Architectural Resources

Mainstream processor architectures and field programmable custom computing machines (FCCMs) are colliding towards a heterogeneous system on chip architecture. This is apparent from Intel and AMD efforts to create new chip architectures with various processing cores focusing on DSP, networking, and graphics. From the embedded processor research, system-on-chips connected by network on chips have allowed scalable architectures with a variety of processing cores connected by an onchip network. In this paper we examine several scheduling and allocation policies that can be utilized across network on chip architectures regardless of the processing cores onchip. By abstracting characteristics of the processing cores with various scheduling data structures, any heterogeneous system on a chip can be allocated and scheduled dynamically.