Specialized Macro-Instructions for Von-Neumann Accelerators

In the last few decades, Von-Neumann super-scalar processors have been the superior approach for improving general purpose processing and hardware specialization was used as a complementary approach. However, the imminent end of Moore’s law indicates voltage scaling and per-transistor switching power can not scale down with the same peace as what Moore’s law predicts. As a result, there is a new interest in hardware specialization to improve performance, power and energy efficiency on specific tasks. Hardware customization so far has effectively targeted programs with abundant parallelism and simple data access patterns using vector extensions, GPUs, and spatial fabrics. However, programs with diverse control and memory behavior have found it challenging to leverage these accelerators. Our work is motivated by observing two main approaches in designing hardware accelerators. First many proposals [45, 20] seem to choose dataflow-based accelerators to reduce front-end energy. However, spatial fabrics encounter challenges with fabric utilization and static power when the available instruction parallelism is below the peak operation parallelism available [14]. Second, using custom or magic instructions[19, 10, 23] integrated with the core pipeline reduces both front-end (fetch and decode) and back-end (register access) costs. The problem with this method is the lack of generality across programs because the desired set of custom instructions varies. This dissertation proposes a Von-Neumann based accelerator, Chainsaw and demonstrates that many of the fundamental overheads (e.g., fetch-decode) can be amortized by adopting the appropriate instruction abstraction. To this end, we use the notion of chains, which are compiler fused sequences of instructions. chains convey the producer-consumer locality between dependent instructions, which the Chainsaw architecture then captures by temporally scheduling such operations on the same execution unit and uses bypass registers to forward the values between dependent operations. Chainsaw is a generic multi-lane architecture (4-stage pipeline per lane) and does not require any specialized compound function units; it can be reloaded enabling it to accelerate multiple program paths. We have developed a complete LLVM-based compiler prototype and simulation infrastructure and demonstrated that an 8-lane Chainsaw is within 73% of the performance of an ideal dataflow architecture while reducing the energy consumption by 45% compared to a 4-way OOO processor.