An All-Digital 12 pJ/Pulse IR-UWB Transmitter Synthesized From a Standard Cell Library

This paper presents an all-digital impulse radio ultra-wideband (IR-UWB) transmitter. All functional blocks in the transmitter are implemented with digital standard cells and automatically place-and-routed by design tools. The center frequency and the bandwidth of the UWB pulses are digitally tuned to compensate for variations, or target different applications. This paper also proposes a calibration scheme and modeling of a cell-based digitally controlled oscillator (DCO), which takes systematic mismatch from automatic place-and-route into account. The transmitter is fabricated in a 65 nm CMOS process, and occupies a core area of 0.032 mm2. The transmitter operates in the 3.1-5.0 GHz UWB band with leakage power of 170 μW and active energy consumption ranges from 8 pJ/pulse to 16 pJ/pulse, which combine to a total minimum energy/pulse of 12 pJ/pulse at 50 Mb/s.

[1]  Salvatore Levantino,et al.  A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[3]  Roberto Nonis,et al.  A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[4]  Brian P. Ginsburg,et al.  Low-Power Impulse UWB Architectures and Circuits , 2009, Proceedings of the IEEE.

[5]  David D. Wentzloff,et al.  A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  David D. Wentzloff,et al.  Delay-Based BPSK for Pulsed-UWB Communication , 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

[7]  Tadashi Maeda,et al.  A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[8]  Chris C. N. Chu,et al.  Fitted Elmore delay: a simple and accurate interconnect delay model , 2002, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Andrew B. Kahng,et al.  Two-pole analysis of interconnection trees , 1995, Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95).

[10]  Andreas F. Molisch,et al.  Spectral shaping of UWB signals for time-hopping impulse radio , 2006, IEEE Journal on Selected Areas in Communications.

[11]  H. Ishikuro,et al.  A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna , 2009, IEEE Journal of Solid-State Circuits.

[12]  Enrique Barajas,et al.  A 75 pJ/bit all-digital quadrature coherent IR-UWB transceiver in 0.18 µm CMOS , 2010, 2010 IEEE Radio Frequency Integrated Circuits Symposium.

[13]  Enrico Temporiti,et al.  A 3.5 GHz Wideband ADPLL With Fractional Spur Suppression Through TDC Dithering and Feedforward Compensation , 2010, IEEE Journal of Solid-State Circuits.

[14]  So-Young Kim,et al.  Closed-Form RC and RLC Delay Models Considering Input Rise Time , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  Lawrence T. Pileggi,et al.  An explicit RC-circuit delay approximation based on the first three moments of the impulse response , 1996, 33rd Design Automation Conference Proceedings, 1996.

[16]  Jan Craninckx,et al.  A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a , 2007, IEEE Journal of Solid-State Circuits.

[17]  Lawrence T. Pileggi,et al.  Modeling the "Effective capacitance" for the RC interconnect of CMOS gates , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Philippe Maurine,et al.  Transition time modeling in deep submicron CMOS , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  A.P. Chandrakasan,et al.  An Energy-Efficient All-Digital UWB Transmitter Employing Dual Capacitively-Coupled Pulse-Shaping Drivers , 2009, IEEE Journal of Solid-State Circuits.

[20]  Mike Shuo-Wei Chen,et al.  A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC , 2010, IEEE Journal of Solid-State Circuits.

[21]  Jan Craninckx,et al.  A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[22]  Un-Ku Moon,et al.  Background calibration techniques for multistage pipelined ADCs with digital redundancy , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[23]  Andrew B. Kahng,et al.  An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..