Optimal Configuration of High-Radix Combined Switches

High-radix switches are an attractive option to improve network performance and to reduce network cost, especially in large switch-based interconnection networks. However, there are some problems related to the integration scale to design such single-chip switches. In this paper we describe an interesting alternative for building high-radix switches which basically consists in combining several current smaller single-chip switches to obtain switches having greater number of ports. This approach is independent of the evolution of single-chip switches and will remain valid as integration scale keeps evolving. We discuss about key design issues of this kind of switches and focus on their internal structure. In order to show the relevance of this issue, we obtain the optimal internal configuration of switches for several networks and evaluate the network performance considering different conditions. Simulation results show that with a correct internal switch design, a network based on these high-radix switches achieves similar performance to a network based on single-chip switches, which have the same number of ports as high-radix switches, and which would be unfeasible with the current integration scale.

[1]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[2]  Pedro López,et al.  Towards an efficient switch architecture for high-radix switches , 2006, 2006 Symposium on Architecture For Networking And Communications Systems.

[3]  Pedro López,et al.  Deterministic versus Adaptive Routing in Fat-Trees , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[4]  Sudhakar Yalamanchili,et al.  Interconnection Networks , 2011, Encyclopedia of Parallel Computing.

[5]  Fabrizio Petrini,et al.  k-ary n-trees: high performance networks for massively parallel architectures , 1997, Proceedings 11th International Parallel Processing Symposium.

[6]  Nick McKeown,et al.  The iSLIP scheduling algorithm for input-queued switches , 1999, TNET.

[7]  Cyriel Minkenberg,et al.  Speculative Flow Control for High-Radix Datacenter Interconnect Routers , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[8]  Cyriel Minkenberg,et al.  Control path implementation for a low-latency optical HPC switch , 2005, 13th Symposium on High Performance Interconnects (HOTI'05).

[9]  William J. Dally,et al.  Microarchitecture of a high radix router , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[10]  Hans Werner Meuer,et al.  Top500 Supercomputer Sites , 1997 .

[11]  William J. Dally,et al.  The BlackWidow High-Radix Clos Network , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[12]  William J. Dally,et al.  Technology-Driven, Highly-Scalable Dragonfly Topology , 2008, 2008 International Symposium on Computer Architecture.

[13]  José Duato,et al.  C-Switches: Increasing Switch Radix with Current Integration Scale , 2011, 2011 IEEE International Conference on High Performance Computing and Communications.

[14]  Sharad Malik,et al.  Power-driven Design of Router Microarchitectures in On-chip Networks , 2003, MICRO.

[15]  Hong Liu,et al.  Energy proportional datacenter networks , 2010, ISCA.

[16]  Cyriel Minkenberg,et al.  Stability degree of switches with finite buffers and non-negligible round-trip time , 2003, Microprocess. Microsystems.