Second generation programmable artificial retina

Lodging a general enough digital processing element (PE) in each pixel of a CMOS imager aims at getting a programmable artificial retina (PAR) that can support fast, compact, low power and low cost vision. Using original architecture and circuit techniques, we have designed and operated a 128/spl times/128 PAR capable of grey-level image processing and pattern recognition with not even 50 transistors per PE.

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