ESD-implant effect on protection capability of NMOS structures

The effect of the so-called ESD-implant was studied and clarified for the complex case of cascoded snapback NMOS structures suitable for 5 V tolerant I/O applications. The critical role of the ESD implant and epi-substrate resistivity on the local maximum temperature during the stress is clarified. Physical process and device numerical analysis was used to gain greater insight into these phenomena.

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