Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET

This paper investigates soft error in memories and logic circuits in 28 nm planar-FDSOI technology by neutron, alpha, proton, and gamma-ray irradiation tests, and compares with SER in bulk-FinFET. The comparison elucidates the different SER trends between planar-FDSOI and bulk-FinFET.

[1]  Philippe Roche,et al.  Technology downscaling worsening radiation effects in bulk: SOI to the rescue , 2013, 2013 IEEE International Electron Devices Meeting.

[2]  Soonyoung Lee,et al.  Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices , 2015, 2015 IEEE International Reliability Physics Symposium.

[3]  S. Incerti,et al.  Geant4 developments and applications , 2006, IEEE Transactions on Nuclear Science.

[4]  Marty R. Shaneyfelt,et al.  Improved capabilities for proton and neutron irradiations at TRIUMF , 2003, 2003 IEEE Radiation Effects Data Workshop.

[5]  Cyril Bottoni,et al.  SER/SEL performances of SRAMs in UTBB FDSOI28 and comparisons with PDSOI and BULK counterparts , 2014, 2014 IEEE International Reliability Physics Symposium.

[6]  Seungbae Lee,et al.  Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

[7]  Ho-Kyu Kang,et al.  The drive currents improvement of FDSOI MOSFETs with undoped Si epitaxial channel and elevated source/drain structure , 2000, 2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125).

[8]  Jongwook Jeon,et al.  Charge-collection modeling for SER simulation in FinFETs , 2016, 2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

[9]  S. Satoh,et al.  CMOS-SRAM soft-error simulation system , 1994, Proceedings of International Workshop on Numerical Modeling of processes and Devices for Integrated Circuits: NUPAD V.

[10]  Taiki Uemura,et al.  Investigation of logic circuit soft error rate (SER) in 14nm FinFET technology , 2016, 2016 IEEE International Reliability Physics Symposium (IRPS).

[11]  Yongsung Ji,et al.  Embedded STT-MRAM in 28-nm FDSOI Logic Process for Industrial MCU/IoT Application , 2018, 2018 IEEE Symposium on VLSI Technology.

[12]  P. Hazucha,et al.  Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .

[13]  R. Ranica,et al.  FDSOI process/design full solutions for ultra low leakage, high speed and low voltage SRAMs , 2013, 2013 Symposium on VLSI Technology.

[14]  Kazuyuki Hirose,et al.  Abnormal increase in soft-error sensitivity of back-biased thin-BOX SOI SRAMs , 2017, 2017 IEEE International Reliability Physics Symposium (IRPS).

[15]  Richard Southwick,et al.  Total Ionizing Dose Radiation Effects on 14 nm FinFET and SOI UTBB Technologies , 2015, 2015 IEEE Radiation Effects Data Workshop (REDW).

[16]  Robert Ecoffet,et al.  Determination of key parameters for SEU occurrence using 3-D full cell SRAM simulations , 1999 .

[17]  Hyeok-Jung Kwon,et al.  Design of the 100 MeV Proton Beam Line for Low Flux Application , 2016 .

[18]  Seungbae Lee,et al.  SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET , 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

[19]  Kazutoshi Kobayashi,et al.  Sensitivity to soft errors of NMOS and PMOS transistors evaluated by latches with stacking structures in a 65 nm FDSOI process , 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).