论文信息 - Silicon Clock Recovery IC's for 2 to 3.5 Gbit/s

Silicon Clock Recovery IC's for 2 to 3.5 Gbit/s

A novel clock recovery IC for Gbit/s optical communication is presented, employing a 1:2 dynamic frequency divider scheme with an external resonator filter. It is based on a conventional Si bipolar process. Two versions of the same IC design are presented, one optimized for 2 to 3 Gbit/s, the other for 3 to 4 Gbit/s. Clock recovery is demonstrated at 2.23 and 3.52 Gbit/s, leading to clock signals of 1.115 and 1.76 GHz, respectively. Measured rms clock phase jitter is less than 0.3°.

B. G. Bosch | U. Langmann | Z. Wang

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