Efficient fault emulation using automatic pre-injection memory access analysis

The complexity of SoCs has been increasing enormously over the last years. This increases the effort for testing the SoCs against natural external influences and fault attacks. These tests require a huge amount of time because of the large fault scenario space. In this paper a novel method is presented on reduction of system test duration. This speed-up is reached by observing memory accesses during a golden model run to find security relevant regions in memories. Therefore, a novel monitor module has been designed and tested which stores the used memory addresses together with the access time stamps.

[1]  Régis Leveugle,et al.  Using run-time reconfiguration for fault injection in hardware prototypes , 2000, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[2]  Leos Kafka Analysis of Applicability of Partial Runtime Reconfiguration in Fault Emulator in Xilinx FPGAs , 2008, 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems.

[3]  Roman Bartosiński,et al.  The LEON3 Processor , 2013 .

[4]  Todd M. Austin,et al.  CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework , 2008, 2008 IEEE International Conference on Computer Design.

[5]  C. Lopez-Ongil,et al.  A Unified Environment for Fault Injection at Any Design Level Based on Emulation , 2007, IEEE Transactions on Nuclear Science.

[6]  Michael Nicolaidis Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[7]  Raimund Ubar,et al.  FPGA based fault emulation of synchronous sequential circuits , 2004, Proceedings Norchip Conference, 2004..

[8]  Yves Crouzet,et al.  MEFISTO-L: a VHDL-based fault injection tool for the experimental assessment of fault tolerance , 1998, Digest of Papers. Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing (Cat. No.98CB36224).

[9]  Christian Steger,et al.  Modular Fault Injector for Multiple Fault Dependability and Security Evaluations , 2011, 2011 14th Euromicro Conference on Digital System Design.

[10]  David Naccache,et al.  The Sorcerer's Apprentice Guide to Fault Attacks , 2006, Proceedings of the IEEE.

[11]  Alfredo Benso,et al.  Fault Injection Techniques and Tools for Embedded Systems , 2003 .

[12]  Massimo Violante,et al.  An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits , 2002, J. Electron. Test..

[13]  J. J. Beahan,et al.  Radiation fault modeling and fault rate estimation for a COTS based space-borne supercomputer , 2002, Proceedings, IEEE Aerospace Conference.

[14]  Johan Karlsson,et al.  Assembly-Level Pre-injection Analysis for Improving Fault Injection Efficiency , 2005, EDCC.

[15]  RAUL BARBOSA Fault Injection Optimization through Assembly-Level Pre-Injection Analysis , 2007 .

[16]  Régis Leveugle,et al.  Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments , 2003, J. Electron. Test..

[17]  Charles E. Stroud,et al.  Embedded Processor Based Fault Injection and SEU Emulation for FPGAs , 2009, ESA.

[18]  Marcus Jeitler,et al.  FuSE - a hardware accelerated HDL fault injection tool , 2009, 2009 5th Southern Conference on Programmable Logic (SPL).