We have developed a 16Mpixel 3D stacked global-shutter CMOS image sensor with pixel level interconnections using 4 million micro bumps. The four photodiodes in the unit pixel circuit on the top substrate share one micro-bump interconnection at a 7.6μm pitch. Each signal of the photodiodes is transferred to the corresponding storage node on the bottom substrate via the interconnection to achieve a global shutter function. Those storage nodes on the bottom substrate are not just protected from incident light but also photo generated carriers. The ratio of the parasitic light sensitivity of an in-pixel storage node and the light sensitivity of a photodiode is -180dB with 3.8μm pixel size, which is smaller than our previous work and prevents any artifact by bright moving objects in the scenes for DSC usage. Introduction Conventional CMOS image sensors widely used in products currently on the market are mainly equipped with a rolling exposure function. This rolling exposure causes so-called “Jell-o effect” distortion when capturing a moving target. A global-shutter image sensor is ideal for digital cameras if the necessary parasitic light sensitivity (PLS), which is the ratio of the light sensitivity of an in-pixel storage node and the light sensitivity of a photodiode, is satisfied with a light-shielded storage node using the 3D stack as we proposed [1]. 3D stacking technologies have been introduced for image sensors [2-4]. Those interconnection technologies, however, set various restrictions on the numbers of interconnections, less than tens of thousands in the case of a less than 10μm pitch, and on the connection area in order to produce a high resolution global shutter image sensor over 10Mpixels. In this paper, we propose a 16Mpixel 3D stacked CMOS image sensor with 4 million interconnections at a 7.6μm pitch that connect every four pixel on the top substrate to the circuits on the bottom substrate without causing any harm to the pixel characteristics and setting a restriction on the interconnection position and area. The architecture of the sensor consists of a storage node for every photo diode to achieve a 16Mpixel global-shutter mode with a PLS of -180dB. Image sensor architecture Fig.1 shows a block diagram of the image sensor.
[1]
C. Van Hoof,et al.
High performance Hybrid and Monolithic Backside Thinned CMOS Imagers realized using a new integration process
,
2006,
2006 International Electron Devices Meeting.
[2]
Hiroshi Takahashi,et al.
A 1/4-inch 8Mpixel back-illuminated stacked CMOS image sensor
,
2013,
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[3]
Joeri De Vos,et al.
Backside illuminated hybrid FPA achieving low cross-talk combined with high QE
,
2011
.
[4]
Yoshiaki Takemoto,et al.
A rolling-shutter distortion-free 3D stacked image sensor with −160dB parasitic light sensitivity in-pixel storage node
,
2013,
2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.