Thermal aware floorplanning incorporating temperature dependent wire delay estimation
暂无分享,去创建一个
Wei Liu | Sarma B. K. Vrudhula | Alberto Nannarelli | Andreas Thor Winther | S. Vrudhula | A. Nannarelli | Wei Liu
[1] Yiyu Shi,et al. Temperature-aware clock tree synthesis considering spatiotemporal hot spot correlations , 2008, 2008 IEEE International Conference on Computer Design.
[2] Sung-Mo Kang,et al. Cell-level placement for improving substrate thermal distribution , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .
[4] C. L. Liu,et al. A New Algorithm for Floorplan Design , 1986, DAC 1986.
[5] Vinod K. Agarwal,et al. The Effect of Technology Scaling on Microarchitectural Structures , 2000 .
[6] Koen De Bosschere,et al. 2FAR: A 2bcgskew Predictor Fused by an Alloyed Redundant History Skewed Perceptron Branch Predictor , 2005, J. Instr. Level Parallelism.
[7] Chia-Pin Chiu,et al. Cooling a Microprocessor Chip , 2006, Proceedings of the IEEE.
[8] Nikil D. Dutt,et al. LEAF: A System Level Leakage-Aware Floorplanner for SoCs , 2007, 2007 Asia and South Pacific Design Automation Conference.
[9] Kevin Skadron,et al. A Case for Thermal-Aware Floorplanning at the Microarchitectural Level , 2005, J. Instr. Level Parallelism.
[10] David Z. Pan,et al. Reliability-aware global routing under thermal considerations , 2009, 2009 1st Asia Symposium on Quality Electronic Design.
[11] David Z. Pan,et al. TACO: temperature aware clock-tree optimization , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[12] Sachin S. Sapatnekar,et al. Thermally-Aware Design , 2008 .
[13] Luca Benini,et al. Dynamic Thermal Clock Skew Compensation using Tunable Delay Buffers , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.
[14] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[15] Israel Koren,et al. Simulated Annealing Based Temperature Aware Floorplanning , 2007, J. Low Power Electron..
[16] Kaustav Banerjee,et al. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Kevin Skadron,et al. HotSpot: a compact thermal modeling methodology for early-stage VLSI design , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[18] Yao-Wen Chang,et al. B*-trees: a new representation for non-slicing floorplans , 2000, Proceedings 37th Design Automation Conference.
[19] J. Black,et al. Electromigration—A brief survey and some recent results , 1969 .
[20] Fadi J. Kurdahi,et al. Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability , 2008, ISQED 2008.
[21] Yao-Wen Chang,et al. Modern floorplanning based on B/sup */-tree and fast simulated annealing , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.