40.3: A 2Gbps/lane Source Synchronous Intra‐Panel Interface for Large Size and High Refresh Rate Panel with Automatic Calibration
暂无分享,去创建一个
Shogo Hachiya | Seiichi Ozawa | Hidetoshi Miura | Masahiro Kato | Shinya Suzuki | Hironobu Akita | Takayuki Murakami | Kazuhisa Sasaki
[1] Hong-June Park,et al. 6.3: A Low-EMI 2Gbps ClockAlignedtoData IntraPanel Interface (CADI) for TFT-LCD with the VSYNC-Embedded Clock and Equalization , 2010 .
[2] Peter A. Franaszek,et al. A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code , 1983, IBM J. Res. Dev..
[3] Deog-Kyoon Jeong,et al. 43.3: Distinguished Paper: An Advanced Intra-Panel Interface (AiPi) with Clock Embedded Multi-Level Point-to-Point Differential Signaling for Large-Sized TFT-LCD Applications , 2006 .
[4] Hwasu Koh. P-39: pLVDS: A New Intra-Panel Interface for the Future Flat-Panel Displays with Higher Resolution and Larger Size , 2009 .
[5] Takashi Nose,et al. 56.1: Invited Paper: A 12‐bit LCD Source Driver IC with Point‐to‐Point Link Interface , 2007 .