ORACLE: optimization with recourse of analog circuits including layout extraction

Long design cycles due to the inability to predict silicon realities is a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for technologies below 100nm, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full custom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remains extremely challenging for nanoscale analog/RF design. We propose an analog/RF circuit design methadology ORACLE, which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and application-specific variables. Concurrently, we demonstrate ORACLE far novel metal-mask configurable designs, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. We also include the silicon validation of the metal-mask configurable designs.

[1]  Georges G. E. Gielen,et al.  Generalized posynomial performance modeling , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[2]  Rob A. Rutenbar,et al.  Synthesis tools for mixed-signal ICs: progress on frontend and backend strategies , 1996, DAC '96.

[3]  Georges G. E. Gielen,et al.  An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits , 2002, DAC '02.

[4]  R. Meyer,et al.  High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages , 1998, IEEE J. Solid State Circuits.

[5]  Rob A. Rutenbar,et al.  Remembrance of circuits past: macromodeling by data mining in large analog design spaces , 2002, DAC '02.

[6]  L.T. Pileggi,et al.  Metal-mask configurable RF front-end circuits , 2004, IEEE Journal of Solid-State Circuits.

[7]  T.H. Lee,et al.  A 1.5 V, 1.5 GHz CMOS low noise amplifier , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[8]  Georges G. E. Gielen,et al.  Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Stephen P. Boyd,et al.  Optimization of inductor circuits via geometric programming , 1999, Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361).

[10]  Thomas H. Lee.  The Design of CMOS Radio-Frequency Integrated Circuits , 1998 .

[11]  C. C. McAndrew,et al.  VBIC95, the vertical bipolar inter-company model , 1996, IEEE J. Solid State Circuits.

[12]  J. L. Showell,et al.  A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design , 1997 .

[13]  Osama Shanaa,et al.  Frequency-scalable SiGe bipolar RF front-end design , 2001 .

[14]  Willy Sansen,et al.  Analog Circuit Design Optimization based on Symbolic Simulation and Simulated Annealing , 1989, ESSCIRC '89: Proceedings of the 15th European Solid-State Circuits Conference.

[15]  Karl Frauendorfer,et al.  Stochastic Two-Stage Programming , 1992 .

[16]  Stephen P. Boyd,et al.  Optimal design of a CMOS op-amp via geometric programming , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Peter Kall,et al.  Stochastic Programming , 1995 .

[18]  Rob A. Rutenbar,et al.  OASYS: a framework for analog circuit synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Stephen P. Boyd,et al.  Convex Optimization , 2004, Algorithms and Theory of Computation Handbook.

[20]  Andrzej J. Strojwas,et al.  Exploring regular fabrics to optimize the performance-cost trade-off , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[21]  Yang Xu,et al.  Metal-mask configurable RF front-end circuits , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

[22]  Joseph Mitola,et al.  Software Radio Architecture: Object-Oriented Approaches to Wireless Systems Engineering , 2000 .