Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield

High defect rate in emerging nano-devices mandates new computational models that can tolerate defects thereby rendering reliability of operation and reasonable manufacturing yield. In a bottom-up system design approach using nano-crossbar applications are typically mapped into a crossbar using either PLA or lookup table (LUT) implementation of a logic circuits. LUT-based implementation has some definite advantages over PLA-based one due its easy reconfigurability. In this paper, we consider a LUT-based logic design paradigm using nano-crossbar and propose a novel application mapping technique that can effectively take advantage of certain defects in the LUTs. The main idea is: 1) to identify and localize the unidirectional stuck-at faults in the LUTs and 2) then map an application in such a way that the a particular defective LUT is used to map a Boolean function which is compatible with the behavior of the LUT. The idea of exploiting certain defects to implement a function (as opposed to discard the defective location as unusable), improves yield considerably in LUT-based configurable nanocomputing. Our simulation with 5times5 and 5times1 LUT shows an average improvement of 87% in number of mapped function over conventional mapping for a defect rate of 10%.

[1]  J. F. Stoddart,et al.  Nanoscale molecular-switch crossbar circuits , 2003 .

[2]  Mark Mohammad Tehranipoor.  Defect tolerance for molecular electronics-based nanofabrics using built-in self-test procedure , 2005, 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05).

[3]  Yoon-Hwa Choi,et al.  A defect-tolerant memory architecture for molecular electronics , 2004 .

[4]  Gang Wang,et al.  On the use of Bloom filters for defect maps in nanocomputing , 2006, ICCAD.

[5]  Fabrizio Lombardi,et al.  On the defect tolerance of nano-scale two-dimensional crossbars , 2004 .

[6]  R. Stanley Williams,et al.  CMOS-like logic in defective, nanoscale crossbars , 2004 .

[7]  Mehdi Baradaran Tahoori,et al.  Defect and fault tolerance of reconfigurable molecular computing , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[8]  André DeHon,et al.  Seven strategies for tolerating highly defective fabrication , 2005, IEEE Design & Test of Computers.

[9]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[10]  Seth Copen Goldstein,et al.  NanoFabrics: spatial computing using molecular electronics , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

[11]  Mircea R. Stan,et al.  CMOS/nano co-design for crossbar-based molecular electronic systems , 2003 .

[12]  R. D. Blanton,et al.  CAEN-BIST: testing the nanofabric , 2004, 2004 International Conferce on Test.

[13]  Mehdi Baradaran Tahoori,et al.  On the defect tolerance of nano-scale two-dimensional crossbars , 2004, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings..

[14]  Mehdi Baradaran Tahoori,et al.  A mapping algorithm for defect-tolerance of reconfigurable nano-architectures , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[15]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[16]  Seth Copen Goldstein,et al.  Defect tolerance at the end of the roadmap , 2003 .

[17]  André DeHon,et al.  Array-based architecture for FET-based, nanoscale electronics , 2003 .