Analog Edge-Filtering Processor Employing Only-Nearest-Neighbor Interconnects

The hardware edge detection system is becoming important for real-time perception applications such as object recognition. However, the hardware edge detecting system realized by massively-parallel processing element architecture has a critical problem called "interconnection explosion." In this study, a new "Only-Nearest-Neighbor Interconnects" architecture has been developed, in which a processing element communicates with only four adjacent cells, realizing a very simple interconnection. Furthermore, the arithmetic operations used in the new architecture involve only two types of calculation: addition and subtraction. These simple calculations have been achieved easily using floating-gate metal-oxide semiconductor (MOS) technology. A test chip was designed and fabricated using 0.35 µm double-poly, triple-metal complementary MOS (CMOS) technology. The experimental results of the edge detection from grayscale images are presented using the core processing elements.