Low-Power High-Speed Small Area Hybrid CMOS Full Adder

A 20-transistor hybrid CMOS full adder circuit using small area transistors has been proposed. The circuit layout is designed with 0.18-μm n-well CMOS design rules. The post layout simulation has been carried out using TSMC018 technology file. The proposed adder circuit provides fully restored logic levels at the output for all input combinations up to an operating frequency of more than 500 MHz. The power dissipation, rise and fall times, and worst-case propagation delay as obtained from the proposed adder have been found to be better in comparison to other full adder circuits (which provide fully restored logic levels at the output) reported in the literature.