An Adaptive Digital Front-End for Multimode Wireless Receivers

The ongoing evolution from 2G to 3G and beyond requires multimode operation of wireless cellular transceivers. This paper discusses the design of an adaptive wireless receiver for multimode operation and power efficiency. This is achieved by sharing digital signal processing stages for all operation modes and adapting them such that performance requirements are met at a minimum power consumption. The flexibility a digital front-end introduces in combination with an analog zero-intermediate-frequency receiver is studied with respect to the main cellular communication standards (Global System for Mobile Communication, Enhanced Data Rates for Global Evolution, Wide-Band Code-Division Multiple Access (WCDMA)/High-Speed Downlink Packet Access, and CDMA2000 and satellite navigation systems (Galileo), with considerations of impacts on the capability of an implementation of a software-defined radio. The proposed approach is verified by simulations exhibiting an error-vector magnitude of 2.9% in Universal Mobile Telecommunications System mode while the estimated power consumption can be reduced by 62% versus full featured mode at reasonable degradation in modulation quality.

[1]  Andrea Baschirotto,et al.  A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  André Bourdoux,et al.  Front-End ADC Requirements for Uniform Bandpass Sampling in SDR , 2007, 2007 IEEE 65th Vehicular Technology Conference - VTC2007-Spring.

[3]  Khurram Muhammad,et al.  Digital RF processing: toward low-cost reconfigurable radios , 2005, IEEE Communications Magazine.

[4]  Shing-Chow Chan,et al.  The design and multiplier-less realization of software radio receivers with reduced system delay , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  T. Ruhlicke,et al.  A single-chip 0.13 /spl mu/m CMOS UMTS W-CDMA multi-band transceiver , 2006, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.

[6]  Minjae Lee,et al.  An 800-MHz–6-GHz Software-Defined Wireless Receiver in 90-nm CMOS , 2006, IEEE Journal of Solid-State Circuits.

[7]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[8]  Tim Hentschel.  Sample rate conversion in software configurable radios , 2002 .

[9]  J. Mitola,et al.  Software radios: Survey, critical evaluation and future directions , 1992, IEEE Aerospace and Electronic Systems Magazine.

[10]  R. Reutemann,et al.  A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[11]  Aleksandar Tasic,et al.  Design of Adaptive Multimode RF Front-End Circuits , 2007, IEEE Journal of Solid-State Circuits.

[12]  Patrizia Greco,et al.  A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-μm CMOS , 2005 .

[13]  F. Kuttner,et al.  A 3-mW 74-dB SNR 2-MHz continuous-time delta-sigma ADC with a tracking ADC quantizer in 0.13-/spl mu/m CMOS , 2005, IEEE Journal of Solid-State Circuits.

[14]  Robert Weigel,et al.  RF system concepts for highly integrated RFICs for W-CDMA mobile radio terminals , 2002 .

[15]  L. Maurer,et al.  A GSM-EDGE/CDMA2000/UMTS Receiver IC for Cellular Terminals in 0.13 μm CMOS , 2006, 2006 European Conference on Wireless Technology.

[16]  Mikko Valkama,et al.  Blind signal estimation in conjugate signal models with application to I/Q imbalance compensation , 2005, IEEE Signal Processing Letters.

[17]  Gernot Hueber,et al.  The design of a multi-mode/multi-system capable software radio receiver , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[18]  Gernot Hueber,et al.  RF Front-End Architecture for Cognitive Radios , 2007, 2007 IEEE 18th International Symposium on Personal, Indoor and Mobile Radio Communications.

[19]  Gernot Hueber,et al.  The Impact of RF-Impairments and Automatic Gain Control on UMTS-HSDPA-Throughput Performance , 2006, IEEE Vehicular Technology Conference.

[20]  A. Dempster,et al.  Use of minimum-adder multiplier blocks in FIR digital filters , 1995 .

[21]  J.R. Long,et al.  Adaptive multi-standard circuits and systems for wireless communications , 2006, IEEE Circuits and Systems Magazine.

[22]  H. Aboushady,et al.  Efficient polyphase decomposition of comb decimation filters in /spl Sigma//spl utri/ analog-to-digital converters , 2001 .

[23]  Lajos Gazsi,et al.  Explicit formulas for lattice wave digital filters , 1985 .

[24]  Jack E. Volder.  The CORDIC Trigonometric Computing Technique , 1959, IRE Trans. Electron. Comput..

[25]  Gernot Hueber,et al.  System Design of a Configurable Highly Digital UMTS/NAVSAT RF-Receiver , 2006, 2006 IEEE 63rd Vehicular Technology Conference.

[26]  Wu-Sheng Lu.  Design of nonlinear-phase FIR digital filters: a semidefinite programming approach , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).

[27]  Sunki Min,et al.  A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications , 2005, IEEE Journal of Solid-State Circuits.