A 300 V//spl mu/s monolithic voltage follower
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An open-loop, JFET input, high-speed buffer, designed without feedback, is described. Careful biasing of source and emitter followers ensures accurate unity gain and gain linearity with 10 mA of load current. A unique quasi-quad input FET layout provides excellent matching and thermal gradient cancellation and simultaneously optimizes speed performance. Offset voltage is permanently adjusted at wafer test by Zener-zap trimming. The output is capable of driving large capacitive loads with 70 mA of peak current.
[1] G. Erdi. A precision trim technique for monolithic analog circuits , 1975, IEEE Journal of Solid-State Circuits.
[2] R. Russell,et al. Ion-implanted JFET-bipolar monolithic analog circuits , 1974 .
[3] J. E. Solomon,et al. The monolithic op amp: a tutorial study , 1974 .