Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs

Different applications concurrently running on modern MPSoCs can interfere with each other when they use shared resources. This interference can cause side channels, i.e., sources of unintended information flow between applications. To prevent such side channels, we propose a hybrid mapping methodology that attempts to ensure spatial isolation, i.e., a mutually-exclusive allocation of resources to applications in the MPSoC. At design time and as a first step, we compute compact and connected application mappings (called shapes). In a second step, run-time management uses this information to map multiple spatially segregated shapes to the architecture. We present and evaluate a (fast) heuristic and an (exact) SAT-based mapper, demonstrating the viability of the approach.

[1]  Henry Hoffmann,et al.  On-Chip Interconnection Architecture of the Tile Processor , 2007, IEEE Micro.

[2]  Majid Sarrafzadeh,et al.  Fast Template Placement for Reconfigurable Computing Systems , 2000, IEEE Des. Test Comput..

[3]  Paul C. Kocher,et al.  Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems , 1996, CRYPTO.

[4]  Michael Glaß,et al.  DAARM: Design-time application analysis and run-time mapping for predictable execution in many-core systems , 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[5]  Richard A. Kemmerer,et al.  Shared resource matrix methodology: an approach to identifying storage and timing channels , 1983, TOCS.

[6]  Amit Kumar Singh,et al.  Mapping on multi/many-core systems: Survey of current and emerging trends , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[7]  Himanshu Kaul,et al.  16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[8]  Benoît Dupont de Dinechin,et al.  A clustered manycore processor architecture for embedded and accelerated applications , 2013, 2013 IEEE High Performance Extreme Computing Conference (HPEC).

[9]  Soonhoi Ha,et al.  Executing synchronous dataflow graphs on a SPM-based multicore architecture , 2012, DAC Design Automation Conference 2012.

[10]  Jörg Henkel,et al.  ADAM: Run-time agent-based distributed application mapping for on-chip communication , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[11]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[12]  Jürgen Teich,et al.  Dynamic decentralized mapping of tree-structured applications on NoC architectures , 2011, Proceedings of the Fifth ACM/IEEE International Symposium.

[13]  Daniel Le Berre,et al.  The Sat4j library, release 2.2 , 2010, J. Satisf. Boolean Model. Comput..

[14]  Amit Kumar Singh,et al.  Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs , 2013, TODE.

[15]  Sanu Mathew,et al.  A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS , 2014, IEEE Journal of Solid-State Circuits.

[16]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[17]  Onur Aciiçmez,et al.  Yet another MicroArchitectural Attack:: exploiting I-Cache , 2007, CSAW '07.

[18]  Michael Glaß,et al.  Towards scalable symbolic routing for multi-objective networked embedded system design and optimization , 2014, 2014 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[19]  Butler W. Lampson,et al.  A note on the confinement problem , 1973, CACM.

[20]  G. Edward Suh,et al.  Efficient Timing Channel Protection for On-Chip Networks , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[21]  Jean-Philippe Diguet,et al.  Move Based Algorithm for Runtime Mapping of Dataflow Actors on Heterogeneous MPSoCs , 2017, J. Signal Process. Syst..

[22]  Jürgen Teich,et al.  Task scheduling for heterogeneous reconfigurable computers , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[23]  Jürgen Becker,et al.  Providing multiple hard latency and throughput guarantees for packet switching networks on chip , 2013, Comput. Electr. Eng..

[24]  Terence D. Todd,et al.  Dynamic slot allocation (DSA) in indoor SDMA/TDMA using smart antenna basestation , 2001, TNET.

[25]  Wei Quan,et al.  A Hybrid Task Mapping Algorithm for Heterogeneous MPSoCs , 2015, ACM Trans. Embed. Comput. Syst..

[26]  Premysl Sucha,et al.  An efficient configuration methodology for time-division multiplexed single resources , 2015, 21st IEEE Real-Time and Embedded Technology and Applications Symposium.

[27]  S. K. Nandy,et al.  Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat , 2015, Circuits Syst. Signal Process..

[28]  Martin Lukasiewycz,et al.  Opt4J: a modular framework for meta-heuristic optimization , 2011, GECCO '11.

[29]  Vincenzo Catania,et al.  A methodology for design of application specific deadlock-free routing algorithms for NoC systems , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[30]  Guy Gogniat,et al.  NOC-centric Security of Reconfigurable SoC , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[31]  Radu Marculescu,et al.  Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[32]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[33]  Lothar Thiele,et al.  Scenario-based design flow for mapping streaming applications onto on-chip many-core systems , 2012, CASES '12.

[34]  J. Jacob,et al.  Basic Theorems About Security , 1992, J. Comput. Secur..

[35]  Alan Burns,et al.  Schedulability analysis and task mapping for real-time on-chip communication , 2010, Real-Time Systems.