Chameleon: A New Multi-Layer Channel Router

New techniques for routing general multi-layer channels are introduced. These techniques can handle a variety of technology constraints. For example, linewidth and line-to-line spacing can be specified independently for each layer, and contact stacking can be allowed or forbidden. These techniques have been implemented in a new multi-layer channel router called Chameleon. Chameleon consists of two stages: a partitioner and a detailed router. The partitioner divides the problem into two and three-layer subproblems such that global channel area is minimized. The detailed router then implements the connections using generalizations of the algorithms used in YACR2. In particular a three-dimensional maze router is used which guarantees that any problem can be routed even when cyclic constraints are present. Chameleon produces optimal results on a wide range of industrial and academic examples for any number of layers and pitch combinations.

[1]  C. Y. Lee An Algorithm for Path Connections and Its Applications , 1961, IRE Trans. Electron. Comput..

[2]  Thomas G. Szymanski Dogleg Channel Routing is NP-Complete , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  R.L. Rivest,et al.  A "Greedy" Channel Router , 1982, 19th Design Automation Conference.

[4]  N. S. Barnett,et al.  Private communication , 1969 .

[5]  Alberto L. Sangiovanni-Vincentelli,et al.  A New Symbolic Channel Router: YACR2 , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  David N. Deutsch A “DOGLEG” channel router , 1976, DAC 1976.

[7]  Yun Kang Chen,et al.  Three-Layer Channel Routing , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Susanne E. Hambrusch Channel Routing Algorithms for Overlap Models , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Takeshi Yoshimura,et al.  Efficient Algorithms for Channel Routing , 1982, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.