A functional test planning system for validation of DSP circuits modeled in VHDL

Validating DSP circuits modeled in VHDL involves generating test data, creating VHDL test benches and simulating the models. This is a laborious and time-consuming process. Therefore, it is desired to develop a high-level approach to automating and planning these tasks. This paper summarizes a high-level test planning system for functional validation of DSP circuits modeled in VHDL. Test data are generated bp VHDL test benches which are created using high-level tools and configured by test plans. The test plans use goal trees to partition the system requirements into partially constrained test groups. The test spaces of the test groups are reduced and so economical tests can be derived. Software tools have been developed based on this approach.