Automatic Functional Stress Pattern Generation for SoC Reliability Characterization

Reliability testing is increasingly used not only to reduce Infant Mortality effects, but also for Reliability Characterization. This paper first discusses the characteristics of the stimuli to be used during Reliability Characterization experiments, and outlines the importance of adopting a functional approach. Secondly, the paper describes a novel approach to automatically generate suitable stress patterns to be used during the Reliability characterization process of Systems-on-chip. The generation process uses an evolutionary algorithm driven by suitable state toggling-related metrics purposely defined in the paper.Costs and benefits of the proposed approach are highlighted, supported by the results gathered on a test vehicle released on a 90nm technology.

[1]  Krishnendu Chakrabarty,et al.  Test-Pattern Ordering for Wafer-Level Test-During-Burn-In , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[2]  A. Benso,et al.  ATPG for Dynamic Burn-In Test in Full-Scan Circuits , 2006, 2006 15th Asian Test Symposium.

[3]  Kuo-Chan Huang,et al.  Maximization of power dissipation under random excitation for burn-in testing , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[4]  O. Semenov,et al.  CMOS IC technology scaling and its impact on burn-in , 2004, IEEE Transactions on Device and Materials Reliability.

[5]  Paolo Bernardi,et al.  An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs , 2008, 2008 13th European Test Symposium.

[6]  Yervant Zorian,et al.  Embedded Processor-Based Self-Test , 2004 .

[7]  Paolo Bernardi,et al.  Using infrastructure IPs to support SW-based self-test of processor cores , 2004, Fifth International Workshop on Microprocessor Test and Verification (MTV'04).

[8]  Giovanni Squillero,et al.  Automatic test program generation: a case study , 2004, IEEE Design & Test of Computers.

[9]  Janak H. Patel,et al.  Cyclic stress tests for full scan circuits , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[10]  Kaushik Roy,et al.  Stress testing of combinational VLSI circuits using existing test sets , 1995, 1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.

[11]  Alessandro Birolini Reliability Engineering: Theory and Practice , 1999 .

[12]  M. Elbert,et al.  Stress testing and reliability , 1994, Conference Record Southcon.