This is a comparative study of the performance of 4-layer and 6-layer FCBGA packages designed to support a high speed DDR1 (double-data rate) interface. Being able to quantify the performance impact in terms of MHz is critical to help decide the cost vs. performance trade-off. A detailed simulation approach, where we were able to translate power distribution network performance into timing impact, is presented. The good correlation between simulations and measurements demonstrates our ability to predict performance and helps improve future decisions based on tradeoffs between cost and performance.