Design of an Interface Circuit in a 2.5Gbps Transceiver System

The interface circuit in a 2.5Gbps transceiver, which consists of a line driver in transmitter and an equalizer in receiver, are designed by using technologies of impedance matching and programmable equalization on-chip. Based on UMC 0.18μm CMOS technological models, the circuit is simulated by Cadence Spectre 's simulators. In the range of 0℃-125℃, the circuit works robustly at ff, tt and ss process comers and in the power supply range of 1.6 V-2.0V. For 1.8V power supply votage, the total power dissipation of the circuit is 70MW.