FPGA Acceleration to Solve Maximum Clique Problems Encoded into Partial MaxSAT

In this paper, we propose an FPGA solver for the maximum clique problems encoded into the partial maximum satisfiability (partial MaxSAT). Given a Boolean formula with hard constraints that required to be satisfied and soft constraints that are desired to be satisfied, the goal of partial MaxSAT is to find a truth assignment that satisfies all hard constraints and as many soft constraints as possible. The maximum clique problem involves finding a clique with the maximum possible number of vertices in a given graph, which can be formulated as partial MaxSAT in a natural way. The Dist algorithm is one of the best performing local search algorithms for solving partial MaxSAT. In this paper, we reconstruct the Dist algorithm to leverage its inherent parallelism while maintaining the accuracy of the algorithm for maximum clique problems and then describe the implementation of the algorithm on FPGA. Our FPGA solver can solve partial MaxSAT-encoded maximum clique problems up to 22 times faster than the Dist algorithm on CPU.