Partitioning around roadblocks: tackling constraints with intermediate relaxations
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[1] R. M. Mattheyses,et al. A Linear-Time Heuristic for Improving Network Partitions , 1982, 19th Design Automation Conference.
[2] Balakrishnan Krishnamurthy,et al. An Improved Min-Cut Algonthm for Partitioning VLSI Networks , 1984, IEEE Transactions on Computers.
[3] Peter Suaris,et al. A quadrisection-based combined place and route scheme for standard cells , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] Chung-Kuan Cheng,et al. An improved two-way partitioning algorithm with stable performance [VLSI] , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Jaeseok Kim,et al. An Efficient Method of Partitioning Circuits for Multiple-FPGA Implementation. , 1993, 30th ACM/IEEE Design Automation Conference.
[6] Krzysztof Kozminski,et al. Cost Minimization of Partitions into Multiple Devices , 1993, 30th ACM/IEEE Design Automation Conference.
[7] Chung-Kuan Cheng,et al. Linear decomposition algorithm for VLSI design applications , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[8] Shantanu Dutt,et al. VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, ICCAD 1996.
[9] Andrew B. Kahng,et al. A hybrid multilevel/genetic approach for circuit partitioning , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.
[10] Shantanu Dutt,et al. A probability-based approach to VLSI circuit partitioning , 1996, DAC '96.
[11] Shashi Shekhar,et al. Multilevel hypergraph partitioning: application in VLSI domain , 1997, DAC.