Synthesizing robust systems

Many specifications include assumptions on the environment. If the environment satisfies the assumptions then a correct system reacts as intended. However, when the environment deviates from its expected behavior, a correct system can behave arbitrarily. We want to synthesize robust systems that degrade gracefully, i.e., a small number of environment failures should induce a small number of system failures. We define ratio games and show that an optimal robust system corresponds to the winning strategy of a ratio game, where the system minimizes the ratio of system errors to environment errors. We show that ratio games can be solved in pseudopolynomial time.

[1]  Amir Pnueli,et al.  Faster Solutions of Rabin and Streett Games , 2006, 21st Annual IEEE Symposium on Logic in Computer Science (LICS'06).

[2]  Krishnendu Chatterjee,et al.  Better Quality in Synthesis through Quantitative Objectives , 2009, CAV.

[3]  Anish Arora,et al.  FTSyn: a framework for automatic synthesis of fault-tolerance , 2008, International Journal on Software Tools for Technology Transfer.

[4]  Viktor Schuppan,et al.  RATSY - A New Requirements Analysis Tool with Synthesis , 2010, CAV.

[5]  Roderick Bloem,et al.  Anzu: A Tool for Property Synthesis , 2007, CAV.

[6]  W. M. Wonham,et al.  The control of discrete event systems , 1989 .

[7]  Amir Pnueli,et al.  Specify, Compile, Run: Hardware from PSL , 2007, COCV@ETAPS.

[8]  Carl E. Landwehr,et al.  Basic concepts and taxonomy of dependable and secure computing , 2004, IEEE Transactions on Dependable and Secure Computing.

[9]  Hugo Gimbert,et al.  Games Where You Can Play Optimally Without Any Memory , 2005, CONCUR.

[10]  Roger G. Schroeder,et al.  Linear Programming Solutions to Ratio Games , 1970, Oper. Res..

[11]  Dejan Nickovic,et al.  Robustness of Sequential Circuits , 2010, 2010 10th International Conference on Application of Concurrency to System Design.

[12]  Sandy Irani,et al.  Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems , 1999, DAC '99.

[13]  Jean-François Raskin,et al.  An Antichain Algorithm for LTL Realizability , 2009, CAV.

[14]  Lorenzo Alvisi,et al.  Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.

[15]  Krishnendu Chatterjee,et al.  Environment Assumptions for Synthesis , 2008, CONCUR.

[16]  Thomas A Henzinger,et al.  Two challenges in embedded systems design: predictability and robustness , 2008, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences.

[17]  Amir Pnueli,et al.  Synthesis of Reactive(1) Designs , 2006, VMCAI.

[18]  Alois Knoll,et al.  Synthesis of Fault-Tolerant Embedded Systems Using Games: From Theory to Practice , 2011, VMCAI.

[19]  Roderick Bloem,et al.  Optimizations for LTL Synthesis , 2006, 2006 Formal Methods in Computer Aided Design.

[20]  Edsger W. Dijkstra,et al.  Self-stabilizing systems in spite of distributed control , 1974, CACM.

[21]  Rolf Drechsler,et al.  A Basis for Formal Robustness Checking , 2008, ISQED 2008.

[22]  Rajeev Alur,et al.  Ranking Automata and Games for Prioritized Requirements , 2008, CAV.

[23]  John C. Knight,et al.  A Framework for Software Fault Tolerance in Real-Time Systems , 1983, IEEE Transactions on Software Engineering.

[24]  Cindy Eisner,et al.  Using Symbolic Model Checking to Verify the Railway Stations of Hoorn-Kersenboogerd and Heerhugowaard , 1999, CHARME.

[25]  Felix C. Gärtner,et al.  Fundamentals of fault-tolerant distributed computing in asynchronous environments , 1999, CSUR.

[26]  Bruce H. Krogh,et al.  Robustness of supervisors for discrete-event systems , 1999, IEEE Trans. Autom. Control..

[27]  Éric Rutten,et al.  Automating the addition of fault tolerance with discrete controller synthesis , 2009, Formal Methods Syst. Des..

[28]  Anish Arora,et al.  Synthesis of fault-tolerant concurrent programs , 2004, TOPL.

[29]  Amir Pnueli,et al.  On the synthesis of a reactive module , 1989, POPL '89.

[30]  Klaus Schneider,et al.  Exploiting the Temporal Logic Hierarchy and the Non-Confluence Property for Efficient LTL Synthesis , 2010, GANDALF.

[31]  Anish Arora,et al.  Synthesis of fault-tolerant concurrent programs , 2004 .

[32]  Yuri Gurevich,et al.  Trees, automata, and games , 1982, STOC '82.

[33]  Uri Zwick,et al.  The Complexity of Mean Payoff Games on Graphs , 1996, Theor. Comput. Sci..

[34]  Deepak D'Souza,et al.  Conflict-Tolerant Features , 2008, CAV.

[35]  Anish Arora,et al.  Closure and Convergence: A Foundation of Fault-Tolerant Computing , 1993, IEEE Trans. Software Eng..

[36]  Gonzalo Navarro,et al.  A guided tour to approximate string matching , 2001, CSUR.

[37]  Alan M. Davis,et al.  Software requirements - analysis and specification , 1990 .

[38]  Amir Pnueli,et al.  Automatic Hardware Synthesis from Specifications: A Case Study , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[39]  Krishnendu Chatterjee,et al.  Robustness in the Presence of Liveness , 2010, CAV.

[40]  Amir Pnueli,et al.  The temporal logic of programs , 1977, 18th Annual Symposium on Foundations of Computer Science (sfcs 1977).

[41]  Ahmed Bouajjani,et al.  Computer aided verification : 21th international conference, CAV 2009, Grenoble, France, June 26-July 2, 2009 : proceedings , 2009, CAV 2009.

[42]  Ali Ebnenasir,et al.  Complexity issues in automated synthesis of failsafe fault-tolerance , 2005, IEEE Transactions on Dependable and Secure Computing.

[43]  Martin C. Rinard,et al.  Acceptability-oriented computing , 2003, OOPSLA '03.

[44]  Krishnendu Chatterjee,et al.  Mean-payoff parity games , 2005, 20th Annual IEEE Symposium on Logic in Computer Science (LICS' 05).