Multiple Event Upsets Aware FPGAs Using Protected Schemes

Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in difierent parts to implement circuit conflguration and to implement circuit data. Moreover, conflguration bits of SRAM- based FPGAs are more sensitive to upsets compared to circuit data due to signiflcant number of SRAM bits. In this paper, a new protected Con- flgurable Logic Block (CLB) and FPGA architecture are proposed which utilize multiple error correction (DEC) and multiple error detection. This is achieved by the incorporation of recently proposed coding technique Matrix codes (1) inside the FPGA. The power and area analysis of the proposed techniques show that these methods are more e-cient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs.